📄 mst_assign.v
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`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: 20:14:31 03/10/2008 // Design Name: // Module Name: MST_assign // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////////////////////////////////////////////////////////////////////////////////////module MST_assign(clk_125, en, resetn, mfi_2, mst_num); input clk_125; input en; input resetn; input [7:0] mfi_2; output [31:0] mst_num; reg [31:0] mst_num;
wire [7:0] a;
assign a=mfi_2%32;always @(posedge clk_125 or negedge resetn)begin:label1 if(!resetn) mst_num<=8'b0000_0000; else if(!en) mst_num<=mst_num; else begin case(a)
8'b0000_0000: mst_num<=32'h0000_0001;
8'b0000_0001: mst_num<=32'h0000_0002;
8'b0000_0010: mst_num<=32'h0000_0004;
8'b0000_0011: mst_num<=32'h0000_0008;
8'b0000_0100: mst_num<=32'h0000_0010; 8'b0000_0101: mst_num<=32'h0000_0020; 8'b0000_0110: mst_num<=32'h0000_0040; 8'b0000_0111: mst_num<=32'h0000_0080;
8'b0000_1000: mst_num<=32'h0000_0100; 8'b0000_1001: mst_num<=32'h0000_0200; 8'b0000_1010: mst_num<=32'h0000_0400; 8'b0000_1011: mst_num<=32'h0000_0800; 8'b0000_1100: mst_num<=32'h0000_1000; 8'b0000_1101: mst_num<=32'h0000_2000; 8'b0000_1110: mst_num<=32'h0000_4000; 8'b0000_1111: mst_num<=32'h0000_8000;
8'b0001_0000: mst_num<=32'h0001_0000; 8'b0001_0001: mst_num<=32'h0002_0000; 8'b0001_0010: mst_num<=32'h0004_0000; 8'b0001_0011: mst_num<=32'h0008_0000; 8'b0001_0100: mst_num<=32'h0010_0000; 8'b0001_0101: mst_num<=32'h0020_0000; 8'b0001_0110: mst_num<=32'h0040_0000; 8'b0001_0111: mst_num<=32'h0080_0000; 8'b0001_1000: mst_num<=32'h0100_0000; 8'b0001_1001: mst_num<=32'h0200_0000; 8'b0001_1010: mst_num<=32'h0400_0000; 8'b0001_1011: mst_num<=32'h0800_0000; 8'b0001_1100: mst_num<=32'h1000_0000; 8'b0001_1101: mst_num<=32'h2000_0000; 8'b0001_1110: mst_num<=32'h4000_0000; 8'b0001_1111: mst_num<=32'h8000_0000; default: mst_num<=32'h0000_0000;
endcase endend endmodule
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