mst_logic_tb.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:03:32 01/05/2008
// Design Name:   MST_logic
// Module Name:   F:/lcas/LCAS/MST_logic_tb.v
// Project Name:  LCAS
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MST_logic
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module MST_logic_tb_v;

	// Inputs
	reg clk_125;
	reg resetn;
	reg en;
	reg [3:0] Ctrl_in;
	
	parameter p_fixed=4'h0;
	parameter p_idle=4'h5;
	parameter p_add=4'h1;
	parameter p_eos=4'h3;
	parameter p_norm=4'h2;
	parameter p_dnu=4'hf;

	// Outputs
	wire Mst_out;

	// Instantiate the Unit Under Test (UUT)
	MST_logic uut (
		.clk_125(clk_125), 
		.resetn(resetn), 
		.en(en), 
		.ctrl_in(Ctrl_in), 
		.Mst_out(Mst_out));
		initial begin
		// Initialize Inputs
		clk_125 = 0;
		resetn = 0;
		en = 0;
		Ctrl_in = 0;

		// Wait 100 ns for global reset to finish
		#100 resetn=1;
		#100 en=1;
		#100 Ctrl_in=p_idle;
		#40  Ctrl_in=p_add;
		#40  Ctrl_in=p_eos;
		#40  Ctrl_in=p_idle;
		#100 Ctrl_in=p_add;
		#40  Ctrl_in=p_eos;
		#40  Ctrl_in=p_norm;
		#40  Ctrl_in=p_eos;
		#40  Ctrl_in=p_dnu;
		#40  Ctrl_in=p_eos;
		#40  Ctrl_in=p_norm;
		#40  Ctrl_in=p_dnu;
		#40  Ctrl_in=p_norm;
		#40  Ctrl_in=p_idle;
		#100 Ctrl_in=p_fixed;
		
		
		#100 en=0;
		#100 resetn=0;
      #100 $stop;
		// Add stimulus here

	end
always #5 clk_125=~clk_125;      
endmodule