rs_ack_so.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:44:21 01/01/2008 
// Design Name: 
// Module Name:    RS_Ack_logic 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module RS_Ack_So(clk_125, resetn, en, RS_Ack_sk, present_ctrl, RS_Ack_out);

//this module receive signal from the sink,RS_Ack
//generator a signal ,sent to VCG controllor 
//confirm the change
    input clk_125;
    input resetn;
    input en;
    input RS_Ack_sk;

	 input [3:0] present_ctrl;
    output RS_Ack_out;
	 reg RS_Ack_out;

    reg RS_Ack_reg;
	 reg [3:0] RS_Ack_counter;
	 reg [3:0] last_ctrl;
	 
	 parameter p_timeout=4'hd;
	 
	 parameter p_add=4'h1;
	 parameter p_eos=4'h3;
	 parameter p_norm=4'h2;
	 parameter p_dnu=4'hf;
	 parameter p_idle=4'h5;
	 

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    RS_Ack_out<=0;
	 else    if(!en)    RS_Ack_out<=RS_Ack_out;
    else    if(RS_Ack_sk^RS_Ack_reg)    RS_Ack_out<=1;
    else    if(RS_Ack_counter==p_timeout)    RS_Ack_out<=1;
    else    RS_Ack_out<=0;	 
end


always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    RS_Ack_reg<=0;
	 else    if(!en)    RS_Ack_reg<=RS_Ack_reg;
	 else    RS_Ack_reg<=RS_Ack_sk;
end

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    last_ctrl<=4'h0;
	 else    if(!en)    last_ctrl<=last_ctrl;
	 else    last_ctrl<=present_ctrl;
end

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    RS_Ack_counter<=4'h0;
	 else    if(!en)    RS_Ack_counter<=RS_Ack_counter;
	 else    if(RS_Ack_out)    RS_Ack_counter<=4'h0;
	 else    if((last_ctrl==p_add)&&((present_ctrl==p_eos)||(present_ctrl==p_norm)))    RS_Ack_counter<=RS_Ack_counter+1'b1;
	 else    if(((last_ctrl==p_norm)||(last_ctrl==p_eos)||(last_ctrl==p_dnu))&&(present_ctrl==p_idle))    RS_Ack_counter<=RS_Ack_counter+1'b1;
	 else    if(RS_Ack_counter!=4'h0)    RS_Ack_counter<=RS_Ack_counter+1'b1;
	 else    RS_Ack_counter<=0;
end
endmodule