ctrl_logic_tf.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:49:57 01/02/2008
// Design Name:   ctrl_logic
// Module Name:   F:/lcas/LCAS/ctrl_logic_tf.v
// Project Name:  LCAS
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ctrl_logic
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module ctrl_logic_tf_v;

	// Inputs
	reg clk_125;
	reg resetn;
	reg en;
	reg Lcas_m;
	reg M_add;
	reg M_rem;
	reg Flag_vcg;
	reg Mst_in;
	reg M_status;
	reg flag_sq;

	// Outputs
	wire [3:0] ctrl_out;
	wire f_vcg;

	// Instantiate the Unit Under Test (UUT)
	ctrl_logic uut (
		.clk_125(clk_125), 
		.resetn(resetn), 
		.en(en), 
		.Lcas_m(Lcas_m), 
		.M_add(M_add), 
		.M_rem(M_rem), 
		.Flag_vcg(Flag_vcg), 
		.Mst_in(Mst_in), 
		.M_status(M_status), 
		.flag_sq(flag_sq), 
		.ctrl_out(ctrl_out), 
		.f_vcg(f_vcg)
	);

	initial begin
		// Initialize Inputs
		clk_125 = 0;
		resetn = 0;
		en = 0;
		Lcas_m = 0;
		M_add = 0;
		M_rem = 0;
		Flag_vcg = 0;
		Mst_in = 0;
		M_status = 0;
		flag_sq = 0;

		// Wait 100 ns for global reset to finish
		#100    resetn=1;
		#20     en=1;
		#20     Lcas_m=1;
		Mst_in=1;
		#20     Flag_vcg=1;
		#40     Flag_vcg=0;
		#100     M_add=1;
		#40     M_status=1;
		Flag_vcg=1;
		//now,the state is ADD,0001
		#40     Mst_in=0;
		M_add=0;
		#40 Flag_vcg=0;
		//now,the state is NORM,0010
		#160     Mst_in=1;
		//now,the state is DNU;1111
		#120     Mst_in=0;
		//now,the state is NORM;0010
		#160     M_rem=1;
		//now,the state is REMOVE;1010
	   #40     Flag_vcg=1;	
		#40     Mst_in=1;
		M_rem=0;
		//now,the state is IDLE;0101
		#150    M_status=0;
		
		
      #100    en=0;
      #50     Lcas_m=0;
		#20     resetn=0;
		
		#100    resetn=1;
		#50     Lcas_m=1;
		#50     en=1;
		Mst_in=1;
		#20     Flag_vcg<=1;
		#40     Flag_vcg=0;
		#100     M_add=1;
		#10     M_status=1;
		Flag_vcg=1;
		//now,the state is ADD
		#30     Mst_in=0;
		M_add=0;
		//now,the state is NORM
		#60     Mst_in=1;
		Flag_vcg=0;
		//now,the state is DNU
		#60    Mst_in=0;
		//now,the state is NORM
		#100     M_rem=1;
		//now,the state is REMOVE
		 #20     Flag_vcg=1;	
		#40     Mst_in=1;
		M_rem=0;
		//now,the state is IDLE
		#150    M_status=0;
		
		
      #100    en=0;
      #50     Lcas_m=0;
		#20     resetn=0;
		
		#100    resetn=1;
		#50     Lcas_m=1;
		#50     en=1;
		Mst_in=1;
		#20     Flag_vcg<=1;
		#40     Flag_vcg=0;
		#100     M_add=1;
		#10     M_status=1;
		Flag_vcg=1;
		//now,the state is ADD
		
		#10     M_rem=1;
		//now,the state is REMOVE
		 #20     Flag_vcg=1;	
		#40     Mst_in=1;
		M_rem=0;
		//now,the state is IDLE
		#150    M_status=0;
		
		
      #100    en=0;
      #50     Lcas_m=0;
		#20     resetn=0;
		#100    $stop;
		// Add stimulus here

	end
always #5 clk_125=~clk_125;

initial 
begin
$monitor($time,"the ctrl out is=%b",ctrl_out);
end
endmodule