📄 timer.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\timer.rpt
timer
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 1/ 96( 1%) 6/ 48( 12%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\timer.rpt
timer
** CLOCK SIGNALS **
Type Fan-out Name
DFF 4 |jiepai:1|74175:17|4Q
INPUT 3 CLKJP
LCELL 3 |jiepai:1|:24
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\timer.rpt
timer
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 3 |jiepai:1|:51
INPUT 3 tj
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\timer.rpt
timer
** EQUATIONS **
CLKJP : INPUT;
DP : INPUT;
QD : INPUT;
tj : INPUT;
-- Node name is 't1'
-- Equation name is 't1', type is output
t1 = _LC4_B1;
-- Node name is 't2'
-- Equation name is 't2', type is output
t2 = _LC8_B1;
-- Node name is 't3'
-- Equation name is 't3', type is output
t3 = _LC2_B10;
-- Node name is 't4'
-- Equation name is 't4', type is output
t4 = _LC1_B10;
-- Node name is '|jiepai:1|:2' = '|jiepai:1|T1'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = LCELL( _EQ001);
_EQ001 = _LC1_B1 & _LC3_B10 & !_LC7_B1;
-- Node name is '|jiepai:1|:3' = '|jiepai:1|T2'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = LCELL( _EQ002);
_EQ002 = !_LC2_B1 & _LC3_B10 & _LC7_B1;
-- Node name is '|jiepai:1|:4' = '|jiepai:1|T3'
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = LCELL( _EQ003);
_EQ003 = _LC2_B1 & _LC3_B10;
-- Node name is '|jiepai:1|:1' = '|jiepai:1|T4'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ004);
_EQ004 = !_LC1_B1 & _LC3_B10;
-- Node name is '|jiepai:1|:24'
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = LCELL( _EQ005);
_EQ005 = _LC3_B1
# CLKJP;
-- Node name is '|jiepai:1|~35~1'
-- Equation name is '_LC5_B10', type is buried
-- synthesized logic cell
_LC5_B10 = LCELL( _EQ006);
_EQ006 = _LC3_B10 & tj
# DP & _LC3_B10;
-- Node name is '|jiepai:1|:36'
-- Equation name is '_LC6_B10', type is buried
!_LC6_B10 = _LC6_B10~NOT;
_LC6_B10~NOT = LCELL( _EQ007);
_EQ007 = _LC4_B10 & !_LC6_B10
# _LC4_B10 & _LC5_B10;
-- Node name is '|jiepai:1|:37'
-- Equation name is '_LC4_B10', type is buried
!_LC4_B10 = _LC4_B10~NOT;
_LC4_B10~NOT = LCELL( QD);
-- Node name is '|jiepai:1|:51'
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ008);
_EQ008 = !_LC3_B1 & !tj
# !CLKJP & !tj;
-- Node name is '|jiepai:1|7474:32|:9' = '|jiepai:1|7474:32|1Q'
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = DFFE( _EQ009, _LC1_B1, GLOBAL(!tj), VCC, VCC);
_EQ009 = _LC4_B10 & _LC6_B10;
-- Node name is '|jiepai:1|7474:46|:9' = '|jiepai:1|7474:46|1Q'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = DFFE( _LC2_B1, GLOBAL(!CLKJP), VCC, VCC, VCC);
-- Node name is '|jiepai:1|74175:17|:15' = '|jiepai:1|74175:17|2Q'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( _LC7_B1, _LC6_B1, _LC5_B1, VCC, VCC);
-- Node name is '|jiepai:1|74175:17|:14' = '|jiepai:1|74175:17|3Q'
-- Equation name is '_LC7_B1', type is buried
_LC7_B1 = DFFE( _LC1_B1, _LC6_B1, _LC5_B1, VCC, VCC);
-- Node name is '|jiepai:1|74175:17|:13' = '|jiepai:1|74175:17|4Q'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( VCC, _LC6_B1, _LC5_B1, VCC, VCC);
Project Information d:\maxplus2\cpu_design\cpu_module\timer.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,878K
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