📄 alu8.rpt
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Project Information d:\maxplus2\cpu_design\cpu_module\alu8.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 09/13/2007 21:36:49
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
alu8 EPF10K10LC84-3 20 9 8 0 0 % 281 48 %
User Pins: 20 9 8
Project Information d:\maxplus2\cpu_design\cpu_module\alu8.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Line 312, File d:\maxplus2\max2lib\mega_lpm\lpm_mult.tdf:
Value of LPM_WIDTHP parameter is too low -- 8 least significant bits of the result have been discarded
Project Information d:\maxplus2\cpu_design\cpu_module\alu8.rpt
** FILE HIERARCHY **
|74244:54|
|74244:55|
|74273:52|
|74273:53|
|74374:48|
|74374:49|
|74374:50|
|74374:51|
|cdu16:11|
|cdu16:11|74161:7|
|cdu16:11|74161:7|f74161:sub|
|cdu16:12|
|cdu16:12|74161:7|
|cdu16:12|74161:7|f74161:sub|
|alu:1|
|alu:1|lpm_or:1|
|alu:1|lpm_and:2|
|alu:1|lpm_mux:3|
|alu:1|lpm_mux:3|altshift:external_latency_ffs|
|alu:1|lpm_mux:3|muxlut:94|
|alu:1|lpm_mux:3|muxlut:112|
|alu:1|lpm_mux:3|muxlut:130|
|alu:1|lpm_mux:3|muxlut:148|
|alu:1|lpm_mux:3|muxlut:166|
|alu:1|lpm_mux:3|muxlut:184|
|alu:1|lpm_mux:3|muxlut:202|
|alu:1|lpm_mux:3|muxlut:220|
|alu:1|lpm_mult:4|
|alu:1|lpm_mult:4|multcore:mult_core|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder1|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_cell:adder0|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_add:sub_csa_add|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_add:sub_csa_add|csa_cell:adder0|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:result_ext_latency_ffs|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:carry_ext_latency_ffs|
|alu:1|lpm_mult:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|altshift:oflow_ext_latency_ffs|
|alu:1|lpm_mult:4|altshift:external_latency_ffs|
|alu:1|lpm_add_sub:5|
|alu:1|lpm_add_sub:5|addcore:adder|
|alu:1|lpm_add_sub:5|altshift:result_ext_latency_ffs|
|alu:1|lpm_add_sub:5|altshift:carry_ext_latency_ffs|
|alu:1|lpm_add_sub:5|altshift:oflow_ext_latency_ffs|
|alu:1|lpm_clshift:39|
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\alu8.rpt
alu8
***** Logic for device 'alu8' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R O
E E A E E E E E N
S S R L V S S G S S S F
E E 3 U C E E N E E E _ ^
R L R _ L _ C R R D R R R # D n
V D V B D B I V c c V I V I V V T O C
E R E U D R U N E l l S E N E N E E C N E
D 1 D S 6 2 S T D r k 0 D T D 5 D D K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | R0_BUS
^nCE | 14 72 | R1_BUS
#TDI | 15 71 | LDR0
t2 | 16 70 | t3
D2 | 17 69 | LDDR1
D0 | 18 68 | GNDINT
D1 | 19 67 | RESERVED
VCCINT | 20 66 | RESERVED
RESERVED | 21 65 | RESERVED
RESERVED | 22 EPF10K10LC84-3 64 | IN0
RESERVED | 23 63 | VCCINT
RESERVED | 24 62 | IN3
RESERVED | 25 61 | CN4
GNDINT | 26 60 | encdu
D4 | 27 59 | IN7
IN6 | 28 58 | D7
D5 | 29 57 | #TMS
IN4 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R L S R L V G R S S V G D I I R R R R
C n E D 2 E D C N 2 W 1 C N 3 N N E E E E
C C S D S R C D _ _ C D 1 2 S S S S
I O E R E 3 I I B B I I E E E E
N N R 2 R N N U U N N R R R R
T F V V T T S S T T V V V V
I E E E E E E
G D D D D D D
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