jie.rpt

简单的CPU设计数字系统实验

                                 Logic cells placed in LAB 'B'
        +----------------------- LC27 Q1
        | +--------------------- LC17 Q2
        | | +------------------- LC18 Q3
        | | | +----------------- LC20 Q4
        | | | | +--------------- LC19 START
        | | | | | +------------- LC22 T1
        | | | | | | +----------- LC23 T2
        | | | | | | | +--------- LC24 T3
        | | | | | | | | +------- LC26 T4
        | | | | | | | | | +----- LC25 ~37~1
        | | | | | | | | | | +--- LC21 ~38~1
        | | | | | | | | | | | +- LC29 |7474:40|1Q
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * - - - - - * * - - - * | - * | <-- Q2
LC18 -> - * - - - * * - - - - - | - * | <-- Q3
LC20 -> - - * - * * - - * - - - | - * | <-- Q4
LC19 -> - - - - - * * * * - * - | - * | <-- START
LC25 -> - - - - * - - - - - * - | - * | <-- ~37~1
LC21 -> - - - - * - - - - - * - | - * | <-- ~38~1
LC29 -> * * * * - - - - - - - - | - * | <-- |7474:40|1Q

Pin
4    -> - - - - - - - - - - * - | - * | <-- DP
7    -> * * * * - - - - - - - * | - * | <-- H
6    -> - - - - - - - - - * - - | - * | <-- QD
5    -> * * * * * - - - - - - - | - * | <-- TJ


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:         d:\maxplus2\cpu_design\cpu_module\jie.rpt
jie

** EQUATIONS **

DP       : INPUT;
H        : INPUT;
QD       : INPUT;
TJ       : INPUT;

-- Node name is 'Q1' = '|74175:42|1Q' 
-- Equation name is 'Q1', type is output 
 Q1      = DFFE( Q2 $  GND,  _EQ001, !_EQ002,  VCC,  VCC);
  _EQ001 =  _X001;
  _X001  = EXP(!H & !_LC029);
  _EQ002 =  _X002 &  _X003;
  _X002  = EXP(!H & !TJ);
  _X003  = EXP(!_LC029 & !TJ);

-- Node name is 'Q2' = '|74175:42|2Q' 
-- Equation name is 'Q2', type is output 
 Q2      = DFFE( Q3 $  GND,  _EQ003, !_EQ004,  VCC,  VCC);
  _EQ003 =  _X001;
  _X001  = EXP(!H & !_LC029);
  _EQ004 =  _X002 &  _X003;
  _X002  = EXP(!H & !TJ);
  _X003  = EXP(!_LC029 & !TJ);

-- Node name is 'Q3' = '|74175:42|3Q' 
-- Equation name is 'Q3', type is output 
 Q3      = DFFE( Q4 $  GND,  _EQ005, !_EQ006,  VCC,  VCC);
  _EQ005 =  _X001;
  _X001  = EXP(!H & !_LC029);
  _EQ006 =  _X002 &  _X003;
  _X002  = EXP(!H & !TJ);
  _X003  = EXP(!_LC029 & !TJ);

-- Node name is 'Q4' = '|74175:42|4Q' 
-- Equation name is 'Q4', type is output 
 Q4      = DFFE( GND $  VCC,  _EQ007, !_EQ008,  VCC,  VCC);
  _EQ007 =  _X001;
  _X001  = EXP(!H & !_LC029);
  _EQ008 =  _X002 &  _X003;
  _X002  = EXP(!H & !TJ);
  _X003  = EXP(!_LC029 & !TJ);

-- Node name is 'START' = '|7474:41|1Q' 
-- Equation name is 'START', type is output 
 START   = DFFE( _EQ009 $  GND,  Q4, !TJ,  VCC,  VCC);
  _EQ009 =  _LC021 &  _LC025;

-- Node name is 'T1' 
-- Equation name is 'T1', location is LC022, type is output.
 T1      = LCELL( _EQ010 $  GND);
  _EQ010 = !Q3 &  Q4 &  START;

-- Node name is 'T2' 
-- Equation name is 'T2', location is LC023, type is output.
 T2      = LCELL( _EQ011 $  GND);
  _EQ011 = !Q2 &  Q3 &  START;

-- Node name is 'T3' 
-- Equation name is 'T3', location is LC024, type is output.
 T3      = LCELL( _EQ012 $  GND);
  _EQ012 =  Q2 &  START;

-- Node name is 'T4' 
-- Equation name is 'T4', location is LC026, type is output.
 T4      = LCELL( _EQ013 $  GND);
  _EQ013 = !Q4 &  START;

-- Node name is '|7474:40|:9' = '|7474:40|1Q' 
-- Equation name is '_LC029', type is buried 
_LC029   = DFFE( Q2 $  GND, !H,  VCC,  VCC,  VCC);

-- Node name is '~37~1' 
-- Equation name is '~37~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL(!QD $  GND);

-- Node name is '~38~1' 
-- Equation name is '~38~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ014 $  VCC);
  _EQ014 =  DP &  _LC025 &  START
         # !_LC021 &  _LC025;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                  d:\maxplus2\cpu_design\cpu_module\jie.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 14,080K