cpurom.vhd

简单的CPU设计数字系统实验

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY cpurom IS
	
	PORT(
		a4,a3,a2,a1,a0	: IN	STD_LOGIC;
		
        move,sw_pc,pc_ar,pc_in,ram_ir_dr,m_ri,ri_m,plus,sub,l_and	:  OUT	STD_LOGIC;
        l_or,mul,m_pc,ram_ar,en_io, ar4,ar3,ar2,ar1,ar0,p1:  OUT	STD_LOGIC);

    END cpurom;

ARCHITECTURE a OF cpurom IS
	SIGNAL sk : STD_LOGIC_VECTOR(4 downto 0);
	SIGNAL sel : STD_LOGIC_VECTOR(20 downto 0);
BEGIN
	
   sk<=a4&a3&a2&a1&a0;
sel<="010000000000000000010"when sk="00000" else
     "001100000000000000100"when sk="00001" else
     "000010000000000100001"when sk="00010" else
     "001100000000000110100"when sk="10001" else-----LDR
     "000000000000001010010"when sk="11010" else
     "000001000000000000010"when sk="01001" else
     "001100000000000110110"when sk="10010" else-----STA
     "000000000000001010100"when sk="11011" else 
     "000000100000000000010"when sk="01010" else
     "000000010000000000010"when sk="10011" else-----PLUS
     "000000001000000000010"when sk="10100" else-----SUB
     "000000000100000000010"when sk="10101" else-----AND
     "000000000010000000010"when sk="10110" else-----OR
     "000000000001000000010"when sk="10111" else-----MUL
     "100000000000000110000"when sk="11111" else-----MOVE
     --"000000000000000111000"when sk="11000" else
     "001100000000000111010"when sk="11001" else-----YMOVE
     "000000000000100000010"when sk="11101" else
     "000100000000000000010"when sk="11000" else-----NMOVE
     "000000000000010000010"when sk="11110" else-----IN_OUT

   
     "000000000000000000";
     


p1<=sel(0);ar4<=sel(5);ar3<=sel(4);ar2<=sel(3);ar1<=sel(2);ar0<=sel(1);ram_ar<=sel(6);move<=sel(20);sw_pc<=sel(19);pc_ar<=sel(18);
pc_in<=sel(17);ram_ir_dr<=sel(16);m_ri<=sel(15);ri_m<=sel(14);
plus<=sel(13);sub<=sel(12);l_and<=sel(11);l_or<=sel(10);
mul<=sel(9);m_pc<=sel(8);en_io<=sel(7);	



END a;