add_sub.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 625 行 · 第 1/2 页
RPT
625 行
21 -> * - - - - - - - - - - - - - - * | - * | <-- a7
41 -> - - - * - - - - - * - - - - - - | - * | <-- b0
16 -> - - - - * - - - - - - - - - - - | - * | <-- b1
14 -> - - - - - * - - - - - - - - - - | - * | <-- b2
13 -> - - - - - - * - - - - - - - - - | - * | <-- b3
12 -> - - - - - - - * - - - - - - - - | - * | <-- b4
11 -> - - - - - - - - * - - - - - - - | - * | <-- b5
5 -> * - - * * * * * * - * * * * * * | * * | <-- s0
LC2 -> * * - - - - - - - - - - - - * * | - * | <-- |LPM_ADD_SUB:27|datab_node6
LC16 -> * - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:27|datab_node7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
s0 : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', location is LC028, type is output.
cout = LCELL( _EQ001 $ _EQ002);
_EQ001 = !s0 & _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008 & _X009
# _LC017 & _X005 & _X006 & _X007 & _X008 & _X009
# _LC029 & _X008 & _X009;
_X001 = EXP(!a0 & !_LC020);
_X002 = EXP(!a1 & !_LC024);
_X003 = EXP(!a2 & !_LC032);
_X004 = EXP(!a3 & !_LC030);
_X005 = EXP(!a4 & !_LC018);
_X006 = EXP(!a5 & !_LC031);
_X007 = EXP(!a6 & !_LC002);
_X008 = EXP( a7 & _LC016);
_X009 = EXP(!a7 & !_LC016);
_EQ002 = a7 & _LC016;
-- Node name is 'r0'
-- Equation name is 'r0', location is LC027, type is output.
r0 = LCELL( b0 $ a0);
-- Node name is 'r1'
-- Equation name is 'r1', location is LC001, type is output.
r1 = LCELL( _EQ003 $ _EQ004);
_EQ003 = a0 & _LC020
# !s0 & _X001;
_X001 = EXP(!a0 & !_LC020);
_EQ004 = _X002 & _X010;
_X002 = EXP(!a1 & !_LC024);
_X010 = EXP( a1 & _LC024);
-- Node name is 'r2'
-- Equation name is 'r2', location is LC019, type is output.
r2 = LCELL( _EQ005 $ _EQ006);
_EQ005 = a0 & _LC020 & _X002
# !s0 & _X001 & _X002
# a1 & _LC024;
_X002 = EXP(!a1 & !_LC024);
_X001 = EXP(!a0 & !_LC020);
_EQ006 = _X003 & _X011;
_X003 = EXP(!a2 & !_LC032);
_X011 = EXP( a2 & _LC032);
-- Node name is 'r3'
-- Equation name is 'r3', location is LC021, type is output.
r3 = LCELL( _EQ007 $ _EQ008);
_EQ007 = a0 & _LC020 & _X002 & _X003
# !s0 & _X001 & _X002 & _X003
# a1 & _LC024 & _X003
# a2 & _LC032;
_X002 = EXP(!a1 & !_LC024);
_X003 = EXP(!a2 & !_LC032);
_X001 = EXP(!a0 & !_LC020);
_EQ008 = _X004 & _X012;
_X004 = EXP(!a3 & !_LC030);
_X012 = EXP( a3 & _LC030);
-- Node name is 'r4'
-- Equation name is 'r4', location is LC022, type is output.
r4 = LCELL( _EQ009 $ _EQ010);
_EQ009 = !s0 & _X001 & _X002 & _X003 & _X004
# _LC017;
_X001 = EXP(!a0 & !_LC020);
_X002 = EXP(!a1 & !_LC024);
_X003 = EXP(!a2 & !_LC032);
_X004 = EXP(!a3 & !_LC030);
_EQ010 = _X005 & _X013;
_X005 = EXP(!a4 & !_LC018);
_X013 = EXP( a4 & _LC018);
-- Node name is 'r5'
-- Equation name is 'r5', location is LC023, type is output.
r5 = LCELL( _EQ011 $ _EQ012);
_EQ011 = !s0 & _X001 & _X002 & _X003 & _X004 & _X005
# a4 & _LC018
# _LC017 & _X005;
_X001 = EXP(!a0 & !_LC020);
_X002 = EXP(!a1 & !_LC024);
_X003 = EXP(!a2 & !_LC032);
_X004 = EXP(!a3 & !_LC030);
_X005 = EXP(!a4 & !_LC018);
_EQ012 = _X006 & _X014;
_X006 = EXP(!a5 & !_LC031);
_X014 = EXP( a5 & _LC031);
-- Node name is 'r6'
-- Equation name is 'r6', location is LC025, type is output.
r6 = LCELL( _EQ013 $ _EQ014);
_EQ013 = !s0 & _X001 & _X002 & _X003 & _X004 & _X005 & _X006
# a4 & _LC018 & _X006
# _LC017 & _X005 & _X006
# a5 & _LC031;
_X001 = EXP(!a0 & !_LC020);
_X002 = EXP(!a1 & !_LC024);
_X003 = EXP(!a2 & !_LC032);
_X004 = EXP(!a3 & !_LC030);
_X005 = EXP(!a4 & !_LC018);
_X006 = EXP(!a5 & !_LC031);
_EQ014 = _X007 & _X015;
_X007 = EXP(!a6 & !_LC002);
_X015 = EXP( a6 & _LC002);
-- Node name is 'r7'
-- Equation name is 'r7', location is LC026, type is output.
r7 = LCELL( _EQ015 $ _EQ016);
_EQ015 = !s0 & _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007
# _LC017 & _X005 & _X006 & _X007
# _LC029;
_X001 = EXP(!a0 & !_LC020);
_X002 = EXP(!a1 & !_LC024);
_X003 = EXP(!a2 & !_LC032);
_X004 = EXP(!a3 & !_LC030);
_X005 = EXP(!a4 & !_LC018);
_X006 = EXP(!a5 & !_LC031);
_X007 = EXP(!a6 & !_LC002);
_EQ016 = _X008 & _X009;
_X008 = EXP( a7 & _LC016);
_X009 = EXP(!a7 & !_LC016);
-- Node name is '|LPM_ADD_SUB:27|addcore:adder|g2cp2' from file "addcore.tdf" line 159, column 9
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( _EQ017 $ GND);
_EQ017 = a4 & _LC018 & _X006 & _X007
# a5 & _LC031 & _X007
# a6 & _LC002;
_X006 = EXP(!a5 & !_LC031);
_X007 = EXP(!a6 & !_LC002);
-- Node name is '|LPM_ADD_SUB:27|addcore:adder|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC017', type is buried
_LC017 = LCELL( _EQ018 $ _EQ019);
_EQ018 = a0 & _LC020 & _X002 & _X003 & _X004 & _X012
# a1 & _LC024 & _X003 & _X004 & _X012
# a2 & _LC032 & _X004 & _X012;
_X002 = EXP(!a1 & !_LC024);
_X003 = EXP(!a2 & !_LC032);
_X004 = EXP(!a3 & !_LC030);
_X012 = EXP( a3 & _LC030);
_EQ019 = a3 & _LC030;
-- Node name is '|LPM_ADD_SUB:27|datab_node0' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( b0 $ !s0);
-- Node name is '|LPM_ADD_SUB:27|datab_node1' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( b1 $ !s0);
-- Node name is '|LPM_ADD_SUB:27|datab_node2' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( b2 $ !s0);
-- Node name is '|LPM_ADD_SUB:27|datab_node3' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( b3 $ !s0);
-- Node name is '|LPM_ADD_SUB:27|datab_node4' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC018', type is buried
_LC018 = LCELL( b4 $ !s0);
-- Node name is '|LPM_ADD_SUB:27|datab_node5' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( b5 $ !s0);
-- Node name is '|LPM_ADD_SUB:27|datab_node6' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC002', type is buried
_LC002 = LCELL( b6 $ !s0);
-- Node name is '|LPM_ADD_SUB:27|datab_node7' from file "lpm_add_sub.tdf" line 112, column 14
-- Equation name is '_LC016', type is buried
_LC016 = LCELL( b7 $ !s0);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, B
-- _X002 occurs in LABs A, B
Project Informationc:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,694K
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?