add_sub.rpt
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RPT
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Project Informationc:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 09/12/2007 16:35:24
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
add_sub EPM7032LC44-6 17 9 0 19 17 59 %
User Pins: 17 9 0
Project Informationc:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
** FILE HIERARCHY **
|lpm_add_sub:27|
|lpm_add_sub:27|addcore:adder|
|lpm_add_sub:27|altshift:result_ext_latency_ffs|
|lpm_add_sub:27|altshift:carry_ext_latency_ffs|
|lpm_add_sub:27|altshift:oflow_ext_latency_ffs|
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
***** Logic for device 'add_sub' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
V G G G G G
a s r C N N N N N b a
1 0 1 C D D D D D 0 0
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
a2 | 7 39 | r2
b7 | 8 38 | RESERVED
b6 | 9 37 | r3
GND | 10 36 | r4
b5 | 11 35 | VCC
b4 | 12 EPM7032LC44-6 34 | r5
b3 | 13 33 | RESERVED
b2 | 14 32 | r6
VCC | 15 31 | r7
b1 | 16 30 | GND
a3 | 17 29 | r0
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
a a a a G V R R R R c
4 5 6 7 N C E E E E o
D C S S S S u
E E E E t
R R R R
V V V V
E E E E
D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 16/16(100%) 3/16( 18%) 7/36( 19%)
B: LC17 - LC32 16/16(100%) 10/16( 62%) 16/16(100%) 25/36( 69%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 26/32 ( 81%)
Total logic cells used: 19/32 ( 59%)
Total shareable expanders used: 17/32 ( 53%)
Total Turbo logic cells used: 19/32 ( 59%)
Total shareable expanders not available (n/a): 2/32 ( 6%)
Average fan-in: 7.00
Total fan-in: 133
Total input pins required: 17
Total output pins required: 9
Total bidirectional pins required: 0
Total logic cells required: 19
Total flipflops required: 0
Total product terms required: 74
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 15
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
40 (18) (B) INPUT 0 0 0 0 0 9 1 a0
6 (3) (A) INPUT 0 0 0 0 0 8 1 a1
7 (4) (A) INPUT 0 0 0 0 0 7 1 a2
17 (12) (A) INPUT 0 0 0 0 0 6 1 a3
18 (13) (A) INPUT 0 0 0 0 0 5 1 a4
19 (14) (A) INPUT 0 0 0 0 0 4 1 a5
20 (15) (A) INPUT 0 0 0 0 0 3 1 a6
21 (16) (A) INPUT 0 0 0 0 0 2 0 a7
41 (17) (B) INPUT 0 0 0 0 0 1 1 b0
16 (11) (A) INPUT 0 0 0 0 0 0 1 b1
14 (10) (A) INPUT 0 0 0 0 0 0 1 b2
13 (9) (A) INPUT 0 0 0 0 0 0 1 b3
12 (8) (A) INPUT 0 0 0 0 0 0 1 b4
11 (7) (A) INPUT 0 0 0 0 0 0 1 b5
9 (6) (A) INPUT 0 0 0 0 0 0 1 b6
8 (5) (A) INPUT 0 0 0 0 0 0 1 b7
5 (2) (A) INPUT 0 0 0 0 0 8 8 s0
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
28 28 B OUTPUT t 9 9 0 9 10 0 0 cout
29 27 B OUTPUT t 0 0 0 2 0 0 0 r0
4 1 A OUTPUT t 3 2 0 3 2 0 0 r1
39 19 B OUTPUT t 4 3 0 4 3 0 0 r2
37 21 B OUTPUT t 6 5 1 5 4 0 0 r3
36 22 B OUTPUT t 6 5 0 6 6 0 0 r4
34 23 B OUTPUT t 7 6 0 7 7 0 0 r5
32 25 B OUTPUT t 9 7 1 8 8 0 0 r6
31 26 B OUTPUT t 9 9 0 9 10 0 0 r7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(27) 29 B SOFT t 2 2 0 3 3 2 0 |LPM_ADD_SUB:27|addcore:adder|g2cp2
(41) 17 B SOFT t 4 4 0 4 4 5 0 |LPM_ADD_SUB:27|addcore:adder|g4
(38) 20 B SOFT t 0 0 0 2 0 8 1 |LPM_ADD_SUB:27|datab_node0
(33) 24 B SOFT t 0 0 0 2 0 8 1 |LPM_ADD_SUB:27|datab_node1
(24) 32 B SOFT t 0 0 0 2 0 7 1 |LPM_ADD_SUB:27|datab_node2
(26) 30 B SOFT t 0 0 0 2 0 6 1 |LPM_ADD_SUB:27|datab_node3
(40) 18 B SOFT t 0 0 0 2 0 5 1 |LPM_ADD_SUB:27|datab_node4
(25) 31 B SOFT t 0 0 0 2 0 4 1 |LPM_ADD_SUB:27|datab_node5
(5) 2 A SOFT t 0 0 0 2 0 3 1 |LPM_ADD_SUB:27|datab_node6
(21) 16 A SOFT t 0 0 0 2 0 2 0 |LPM_ADD_SUB:27|datab_node7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC2 |LPM_ADD_SUB:27|datab_node6
| +--- LC16 |LPM_ADD_SUB:27|datab_node7
| | +- LC1 r1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B | Logic cells that feed LAB 'A':
Pin
40 -> - - * | * * | <-- a0
6 -> - - * | * * | <-- a1
9 -> * - - | * - | <-- b6
8 -> - * - | * - | <-- b7
5 -> * * * | * * | <-- s0
LC20 -> - - * | * * | <-- |LPM_ADD_SUB:27|datab_node0
LC24 -> - - * | * * | <-- |LPM_ADD_SUB:27|datab_node1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:c:\documents and settings\user\cpu_design\cpu_module\add_sub.rpt
add_sub
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC28 cout
| +----------------------------- LC29 |LPM_ADD_SUB:27|addcore:adder|g2cp2
| | +--------------------------- LC17 |LPM_ADD_SUB:27|addcore:adder|g4
| | | +------------------------- LC20 |LPM_ADD_SUB:27|datab_node0
| | | | +----------------------- LC24 |LPM_ADD_SUB:27|datab_node1
| | | | | +--------------------- LC32 |LPM_ADD_SUB:27|datab_node2
| | | | | | +------------------- LC30 |LPM_ADD_SUB:27|datab_node3
| | | | | | | +----------------- LC18 |LPM_ADD_SUB:27|datab_node4
| | | | | | | | +--------------- LC31 |LPM_ADD_SUB:27|datab_node5
| | | | | | | | | +------------- LC27 r0
| | | | | | | | | | +----------- LC19 r2
| | | | | | | | | | | +--------- LC21 r3
| | | | | | | | | | | | +------- LC22 r4
| | | | | | | | | | | | | +----- LC23 r5
| | | | | | | | | | | | | | +--- LC25 r6
| | | | | | | | | | | | | | | +- LC26 r7
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC29 -> * - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:27|addcore:adder|g2cp2
LC17 -> * - - - - - - - - - - - * * * * | - * | <-- |LPM_ADD_SUB:27|addcore:adder|g4
LC20 -> * - * - - - - - - - * * * * * * | * * | <-- |LPM_ADD_SUB:27|datab_node0
LC24 -> * - * - - - - - - - * * * * * * | * * | <-- |LPM_ADD_SUB:27|datab_node1
LC32 -> * - * - - - - - - - * * * * * * | - * | <-- |LPM_ADD_SUB:27|datab_node2
LC30 -> * - * - - - - - - - - * * * * * | - * | <-- |LPM_ADD_SUB:27|datab_node3
LC18 -> * * - - - - - - - - - - * * * * | - * | <-- |LPM_ADD_SUB:27|datab_node4
LC31 -> * * - - - - - - - - - - - * * * | - * | <-- |LPM_ADD_SUB:27|datab_node5
Pin
40 -> * - * - - - - - - * * * * * * * | * * | <-- a0
6 -> * - * - - - - - - - * * * * * * | * * | <-- a1
7 -> * - * - - - - - - - * * * * * * | - * | <-- a2
17 -> * - * - - - - - - - - * * * * * | - * | <-- a3
18 -> * * - - - - - - - - - - * * * * | - * | <-- a4
19 -> * * - - - - - - - - - - - * * * | - * | <-- a5
20 -> * * - - - - - - - - - - - - * * | - * | <-- a6
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