test_ram.hif

简单的CPU设计数字系统实验

HIF003
--
-- Copyright (C) 1988-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	74244.gdf
	{
		74244 [] []
		{
			1 [] [];
		}
	}
	74273.gdf
	{
		74273 [] []
		{
			2 [] [];
		}
	}
	74161.tdf
	{
		74161 [DEVICE_FAMILY,USE_LPM_FOR_AHDL_OPERATORS] [aglobal.inc]
		{
			3 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [LDN,A,QD,QC,QB,QA,ENT,D,C,B,CLRN,CLK,ENP];
			5 [DEVICE_FAMILY=FLEX10K,USE_LPM_FOR_AHDL_OPERATORS=OFF] [LDN,A,QD,QC,QB,QA,ENT,D,C,B,RCO,CLRN,CLK,ENP];
		}
	}
	lpm_ram_io.tdf
	{
		lpm_ram_io [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_WIDTHAD,LPM_NUMWORDS,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=REGISTERED,LPM_FILE=NO_FILE,DEVICE_FAMILY] [aglobal.inc,lpm_decode.inc,lpm_mux.inc,altram.inc]
		{
			34 [DEVICE_FAMILY=FLEX10K,LPM_FILE="e:\cpu_design\cpumodel\uprog00.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
			32 [DEVICE_FAMILY=FLEX10K,LPM_FILE="e:\cpu_design\cpumodel\upr.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
			28 [DEVICE_FAMILY=FLEX10K,LPM_FILE="e:\cpu_design\cpumodel\uprog.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
			8 [DEVICE_FAMILY=FLEX10K,LPM_FILE="d:\maxplus2\cpu_design\cpu_module\prog.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
			17 [DEVICE_FAMILY=FLEX10K,LPM_FILE="c:\maxplus2\vv\07\prog.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
			15 [DEVICE_FAMILY=FLEX10K,LPM_FILE="d:\maxplus2\07\prog.mif",LPM_OUTDATA=UNREGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_INDATA=REGISTERED,LPM_NUMWORDS=256,LPM_WIDTHAD=8,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [dio0,dio1,dio2,dio3,dio4,dio5,dio6,dio7,outenab,we,inclock,memenab,address0,address1,address2,address3,address4,address5,address6,address7];
			6 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE=NO_FILE,DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
			19 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="d:\maxplus2\07\prog1.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
			21 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="c:\maxplus2\vv\07\prog1.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
			24 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="d:\maxplus2\cpu_design\cpu_model\prog.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
			26 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="d:\maxplus2\cpu_model0\uprog.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
			30 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="e:\cpu_design\cpumodel\prog0.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
			36 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=8,LPM_WIDTHAD=8,LPM_NUMWORDS=256,LPM_INDATA=REGISTERED,LPM_ADDRESS_CONTROL=REGISTERED,LPM_OUTDATA=UNREGISTERED,LPM_FILE="c:\documents and settings\user\cpumodel\uprog00.mif",DEVICE_FAMILY=FLEX10K] [address7,address6,address5,address4,address3,address2,address1,address0,memenab,inclock,we,outenab,dio7,dio6,dio5,dio4,dio3,dio2,dio1,dio0];
		}
	}
	f74161.gdf
	{
		f74161 [] []
		{
			4 [] [];
		}
	}
	altram.tdf
	{
		altram [USE_LPM_FOR_AHDL_OPERATORS,WIDTH,AD_WIDTH,NUMWORDS,FILE=NO_FILE,REGISTERINPUTMODE=DEFAULT,USE_EAB=ON,DEVICE_FAMILY] [aglobal.inc,lpm_mux.inc,lpm_decode.inc,memmodes.inc]
		{
			35 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="e:\cpu_design\cpumodel\uprog00.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
			33 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="e:\cpu_design\cpumodel\upr.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
			29 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="e:\cpu_design\cpumodel\uprog.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
			23 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="d:\maxplus2\cpu_design\cpu_module\prog.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
			18 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="c:\maxplus2\vv\07\prog.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
			16 [DEVICE_FAMILY=FLEX10K,USE_EAB=ON,REGISTERINPUTMODE=ALL,FILE="d:\maxplus2\07\prog.mif",NUMWORDS=256,AD_WIDTH=8,WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0,WE,Data7,Data6,Data5,Data4,Data3,Data2,Data1,Data0,Address7,Address6,Address5,Address4,Address3,Address2,Address1,Address0,ClockI];
			7 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE=NO_FILE,REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
			20 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE="d:\maxplus2\07\prog1.mif",REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
			22 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE="c:\maxplus2\vv\07\prog1.mif",REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
			25 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE="d:\maxplus2\cpu_design\cpu_model\prog.mif",REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
			27 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE="d:\maxplus2\cpu_model0\uprog.mif",REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
			31 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE="e:\cpu_design\cpumodel\prog0.mif",REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
			37 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=8,AD_WIDTH=8,NUMWORDS=256,FILE="c:\documents and settings\user\cpumodel\uprog00.mif",REGISTERINPUTMODE=ALL,USE_EAB=ON,DEVICE_FAMILY=FLEX10K] [ClockI,Address0,Address1,Address2,Address3,Address4,Address5,Address6,Address7,Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,WE,Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7];
		}
	}
	74151.tdf
	{
		74151 [USE_LPM_FOR_AHDL_OPERATORS,DEVICE_FAMILY] [aglobal.inc]
		{
			10 [USE_LPM_FOR_AHDL_OPERATORS=OFF,DEVICE_FAMILY=FLEX10K] [GN,A,B,C,D1,D0,D5,D4,D3,D2,D7,D6,Y];
		}
	}
	f74151.gdf
	{
		f74151 [] []
		{
			11 [] [];
		}
	}
	7449.gdf
	{
		7449 [] []
		{
			12 [] [];
		}
	}
	74175.gdf
	{
		74175 [] []
		{
			14 [] [];
		}
	}
	scan.gdf
	{
		scan [] []
		{
			13 [] [];
		}
	}
	bed_7seg.gdf
	{
		bed_7seg [] []
		{
			9 [] [];
		}
	}
	test_ram.gdf
	{
		test_ram [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	test_ram::(0,0):(0): test_ram.gdf
	{
		74244:1:(0,0):(125): 74244.gdf;
		lpm_ram_io:34:(0,0):(81): lpm_ram_io.tdf
		{
			altram:37:(92,5):(48,sram): altram.tdf;
		}
		74161:5:(0,0):(75): 74161.tdf
		{
			f74161:4:(33,3):(41,sub): f74161.gdf;
		}
		74161:3:(0,0):(74): 74161.tdf
		{
			f74161:4:(33,3):(41,sub): f74161.gdf;
		}
		74273:2:(0,0):(78): 74273.gdf;
	}
}