simple.tdf

简单的CPU设计数字系统实验

SUBDESIGN simple
(
   clk, d : INPUT;
   q                  : OUTPUT;
)

VARIABLE
   ss: MACHINE WITH STATES (s0, s1);

BEGIN

   ss.clk = clk;
   %ss.reset = reset;%
   %ss.ena = ena;%

   CASE ss IS
      WHEN s0 =>
         q = GND;

         IF d THEN
            ss = s1;
         END IF;
      WHEN s1 =>
         q = VCC;

         IF !d THEN
            ss = s0;
         END IF;
   END CASE;

END;