kong_sim.rpt

来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 864 行 · 第 1/3 页

-- Equation name is 'ldir', type is output 
 ldir    = DFFE( _EQ032 $  GND,  _EQ033, GLOBAL( CLR),  VCC,  VCC);
  _EQ032 = !a0 &  a1 & !a2 & !a3 & !a4;
  _EQ033 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'move' = '|74273:39|Q7' 
-- Equation name is 'move', type is output 
 move    = DFFE( _EQ034 $  GND,  _EQ035, GLOBAL( CLR),  VCC,  VCC);
  _EQ034 =  a0 &  a1 &  a2 &  a3 &  a4;
  _EQ035 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'pc_bus' = '|74273:40|Q7' 
-- Equation name is 'pc_bus', type is output 
 pc_bus  = DFFE( _EQ036 $  VCC,  _EQ037, GLOBAL( CLR),  VCC,  VCC);
  _EQ036 = !a0 &  a1 & !a2 & !a3 &  a4
         #  a0 & !a1 & !a2 &  a4
         #  a0 & !a1 & !a2 & !a3;
  _EQ037 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'P1' = '|74273:39|Q6' 
-- Equation name is 'P1', type is output 
 P1      = DFFE( _EQ038 $  GND,  _EQ039, GLOBAL( CLR),  VCC,  VCC);
  _EQ038 = !a0 &  a1 & !a2 & !a3 & !a4;
  _EQ039 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'r_bus' = '|74273:38|Q2' 
-- Equation name is 'r_bus', type is output 
 r_bus   = DFFE( _EQ040 $  VCC,  _EQ041, GLOBAL( CLR),  VCC,  VCC);
  _EQ040 = !a0 &  a1 & !a2 &  a3 & !a4;
  _EQ041 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'RD' = '|74273:40|Q5' 
-- Equation name is 'RD', type is output 
 RD      = DFFE( _EQ042 $  GND,  _EQ043, GLOBAL( CLR),  VCC,  VCC);
  _EQ042 =  a0 & !a1 &  a2 &  a3 &  a4
         #  a0 & !a1 & !a2 &  a3 & !a4
         # !a0 &  a1 & !a2 & !a3 & !a4
         #  a1 & !a2 &  a3 &  a4;
  _EQ043 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'r_load' = '|74273:39|Q8' 
-- Equation name is 'r_load', type is output 
 r_load  = DFFE( _EQ044 $  GND,  _EQ045, GLOBAL( CLR),  VCC,  VCC);
  _EQ044 =  a0 &  a1 & !a3 &  a4
         #  a2 & !a3 &  a4;
  _EQ045 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'sw_bus' = '|74273:40|Q3' 
-- Equation name is 'sw_bus', type is output 
 sw_bus  = DFFE( _EQ046 $  VCC,  _EQ047, GLOBAL( CLR),  VCC,  VCC);
  _EQ046 = !a0 & !a1 & !a2 & !a3 & !a4;
  _EQ047 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 's0' = '|74273:38|Q4' 
-- Equation name is 's0', type is output 
 s0      = DFFE( _EQ048 $  GND,  _EQ049, GLOBAL( CLR),  VCC,  VCC);
  _EQ048 =  a1 &  a2 & !a3 &  a4;
  _EQ049 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 's1' = '|74273:38|Q5' 
-- Equation name is 's1', type is output 
 s1      = DFFE( _EQ050 $  GND,  _EQ051, GLOBAL( CLR),  VCC,  VCC);
  _EQ050 = !a0 &  a1 &  a2 & !a3 &  a4
         #  a0 & !a1 &  a2 & !a3 &  a4;
  _EQ051 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 's2' = '|74273:38|Q6' 
-- Equation name is 's2', type is output 
 s2      = DFFE( _EQ052 $  GND,  _EQ053, GLOBAL( CLR),  VCC,  VCC);
  _EQ052 =  a0 &  a1 & !a2 & !a3 &  a4;
  _EQ053 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'T1' 
-- Equation name is 'T1', location is LC027, type is output.
 T1      = LCELL( _EQ054 $  GND);
  _EQ054 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'T2' 
-- Equation name is 'T2', location is LC025, type is output.
 T2      = LCELL( _EQ055 $  GND);
  _EQ055 =  _LC055 &  _LC057;

-- Node name is 'T3' 
-- Equation name is 'T3', location is LC060, type is output.
 T3      = LCELL( _EQ056 $  GND);
  _EQ056 =  _LC057 & !_LC058;

-- Node name is 't4' 
-- Equation name is 't4', location is LC059, type is output.
 t4      = LCELL( _EQ057 $  GND);
  _EQ057 =  _LC057 &  _LC058 & !_LC063;

-- Node name is 'we' = '|74273:40|Q4' 
-- Equation name is 'we', type is output 
 we      = DFFE( _EQ058 $  GND,  _EQ059, GLOBAL( CLR),  VCC,  VCC);
  _EQ058 = !a0 &  a1 & !a2 &  a3 & !a4;
  _EQ059 = !_LC055 &  _LC057 &  _LC063;

-- Node name is '161clrn' = '|74273:39|Q1' 
-- Equation name is '161clrn', type is output 
 161clrn = DFFE( GND $  VCC,  _EQ060, GLOBAL( CLR),  VCC,  VCC);
  _EQ060 = !_LC055 &  _LC057 &  _LC063;

-- Node name is '161load' = '|74273:39|Q2' 
-- Equation name is '161load', type is output 
 161load = DFFE( _EQ061 $  GND,  _EQ062, GLOBAL( CLR),  VCC,  VCC);
  _EQ061 = !a0 & !a1 &  a2 &  a3 &  a4
         # !a0 &  a1 & !a2 & !a3 &  a4
         #  a0 & !a1 & !a2 &  a4
         #  a0 & !a1 & !a2 & !a3;
  _EQ062 = !_LC055 &  _LC057 &  _LC063;

-- Node name is '161pc' = '|74273:40|Q8' 
-- Equation name is '161pc', type is output 
 161pc   = DFFE( _EQ063 $  GND,  _EQ064, GLOBAL( CLR),  VCC,  VCC);
  _EQ063 = !a0 &  a1 & !a2 & !a3 &  a4
         # !a1 &  a2 &  a3 &  a4
         #  a0 & !a1 & !a2 &  a4
         # !a1 & !a2 & !a3 & !a4;
  _EQ064 = !_LC055 &  _LC057 &  _LC063;

-- Node name is '|jie:101|~37~1' 
-- Equation name is '_LC031', type is buried 
-- synthesized logic cell 
_LC031   = LCELL(!QD $  GND);

-- Node name is '|jie:101|~38~1' 
-- Equation name is '_LC050', type is buried 
-- synthesized logic cell 
_LC050   = LCELL( _EQ065 $  VCC);
  _EQ065 =  DP &  _LC031 &  _LC057
         #  _LC031 & !_LC050;

-- Node name is '|jie:101|7474:40|:9' = '|jie:101|7474:40|1Q' 
-- Equation name is '_LC062', type is buried 
_LC062   = DFFE( _LC055 $  GND, !H,  VCC,  VCC,  VCC);

-- Node name is '|jie:101|7474:41|:9' = '|jie:101|7474:41|1Q' 
-- Equation name is '_LC057', type is buried 
_LC057   = DFFE( _EQ066 $  GND,  _LC058, !TJ,  VCC,  VCC);
  _EQ066 =  _LC031 &  _LC050;

-- Node name is '|jie:101|74175:42|:15' = '|jie:101|74175:42|2Q' 
-- Equation name is '_LC055', type is buried 
_LC055   = DFFE( _LC063 $  GND,  _EQ067, !_EQ068,  VCC,  VCC);
  _EQ067 =  _X008;
  _X008  = EXP(!H & !_LC062);
  _EQ068 =  _X009 &  _X010;
  _X009  = EXP(!H & !TJ);
  _X010  = EXP(!_LC062 & !TJ);

-- Node name is '|jie:101|74175:42|:14' = '|jie:101|74175:42|3Q' 
-- Equation name is '_LC063', type is buried 
_LC063   = DFFE( _LC058 $  GND,  _EQ069, !_EQ070,  VCC,  VCC);
  _EQ069 =  _X008;
  _X008  = EXP(!H & !_LC062);
  _EQ070 =  _X009 &  _X010;
  _X009  = EXP(!H & !TJ);
  _X010  = EXP(!_LC062 & !TJ);

-- Node name is '|jie:101|74175:42|:13' = '|jie:101|74175:42|4Q' 
-- Equation name is '_LC058', type is buried 
_LC058   = DFFE( GND $  VCC,  _EQ071, !_EQ072,  VCC,  VCC);
  _EQ071 =  _X008;
  _X008  = EXP(!H & !_LC062);
  _EQ072 =  _X009 &  _X010;
  _X009  = EXP(!H & !TJ);
  _X010  = EXP(!_LC062 & !TJ);

-- Node name is '|74273:41|:15' = '|74273:41|Q5' 
-- Equation name is '_LC034', type is buried 
_LC034   = DFFE( IR7 $  GND,  _EQ073, GLOBAL( CLR),  VCC,  VCC);
  _EQ073 =  _LC055 &  _LC057;

-- Node name is '|74273:41|:14' = '|74273:41|Q6' 
-- Equation name is '_LC042', type is buried 
_LC042   = DFFE( IR6 $  GND,  _EQ074, GLOBAL( CLR),  VCC,  VCC);
  _EQ074 =  _LC055 &  _LC057;

-- Node name is '|74273:41|:13' = '|74273:41|Q7' 
-- Equation name is '_LC039', type is buried 
_LC039   = DFFE( IR5 $  GND,  _EQ075, GLOBAL( CLR),  VCC,  VCC);
  _EQ075 =  _LC055 &  _LC057;

-- Node name is '|74273:41|:12' = '|74273:41|Q8' 
-- Equation name is '_LC047', type is buried 
_LC047   = DFFE( IR4 $  GND,  _EQ076, GLOBAL( CLR),  VCC,  VCC);
  _EQ076 =  _LC055 &  _LC057;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                        e:\cpu_design\cpumodel\kong_sim.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,643K