kong_sim.rpt

来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 864 行 · 第 1/3 页

   -     34    C       DFFE      t        0      0   0    1    2    1    0  |74273:41|Q5 (|74273:41|:15)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:               e:\cpu_design\cpumodel\kong_sim.rpt
kong_sim

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC29 en
        | +------------------- LC31 |jie:101|~37~1
        | | +----------------- LC17 s0
        | | | +--------------- LC28 s1
        | | | | +------------- LC19 s2
        | | | | | +----------- LC27 T1
        | | | | | | +--------- LC25 T2
        | | | | | | | +------- LC24 we
        | | | | | | | | +----- LC22 161clrn
        | | | | | | | | | +--- LC21 161load
        | | | | | | | | | | +- LC20 161pc
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':

Pin
1    -> - - - - - - - - - - - | - - - - | <-- CLR
8    -> - * - - - - - - - - - | - * - - | <-- QD
LC49 -> * - - * * - - * - * * | - * * * | <-- a0
LC51 -> * - * * * - - * - * * | - * * * | <-- a1
LC53 -> * - * * * - - * - * * | - * * * | <-- a2
LC52 -> * - * * * - - * - * * | - * * * | <-- a3
LC54 -> * - * * * - - * - * * | - * * * | <-- a4
LC57 -> - - * * * * * * * * * | - * * * | <-- |jie:101|7474:41|1Q
LC63 -> - - * * * * - * * * * | - * * * | <-- |jie:101|74175:42|3Q
LC55 -> - - * * * * * * * * * | - * * * | <-- |jie:101|74175:42|2Q


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\cpu_design\cpumodel\kong_sim.rpt
kong_sim

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC43 ldar
        | +----------------------------- LC45 lddr
        | | +--------------------------- LC46 lddr1
        | | | +------------------------- LC48 lddr2
        | | | | +----------------------- LC44 ldir
        | | | | | +--------------------- LC40 move
        | | | | | | +------------------- LC37 pc_bus
        | | | | | | | +----------------- LC33 P1
        | | | | | | | | +--------------- LC38 r_bus
        | | | | | | | | | +------------- LC36 RD
        | | | | | | | | | | +----------- LC35 r_load
        | | | | | | | | | | | +--------- LC41 sw_bus
        | | | | | | | | | | | | +------- LC47 |74273:41|Q8
        | | | | | | | | | | | | | +----- LC39 |74273:41|Q7
        | | | | | | | | | | | | | | +--- LC42 |74273:41|Q6
        | | | | | | | | | | | | | | | +- LC34 |74273:41|Q5
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':

Pin
1    -> - - - - - - - - - - - - - - - - | - - - - | <-- CLR
14   -> - - - - - - - - - - - - * - - - | - - * - | <-- IR4
15   -> - - - - - - - - - - - - - * - - | - - * - | <-- IR5
17   -> - - - - - - - - - - - - - - * - | - - * - | <-- IR6
18   -> - - - - - - - - - - - - - - - * | - - * - | <-- IR7
LC49 -> * * * * * * * * * * * * - - - - | - * * * | <-- a0
LC51 -> * * * * * * * * * * * * - - - - | - * * * | <-- a1
LC53 -> * * * * * * * * * * * * - - - - | - * * * | <-- a2
LC52 -> * * * * * * * * * * * * - - - - | - * * * | <-- a3
LC54 -> * * * * * * * * * * * * - - - - | - * * * | <-- a4
LC57 -> * * * * * * * * * * * * * * * * | - * * * | <-- |jie:101|7474:41|1Q
LC63 -> * * * * * * * * * * * * - - - - | - * * * | <-- |jie:101|74175:42|3Q
LC55 -> * * * * * * * * * * * * * * * * | - * * * | <-- |jie:101|74175:42|2Q


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\cpu_design\cpumodel\kong_sim.rpt
kong_sim

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC61 alu_bus
        | +----------------------------- LC49 a0
        | | +--------------------------- LC51 a1
        | | | +------------------------- LC53 a2
        | | | | +----------------------- LC52 a3
        | | | | | +--------------------- LC54 a4
        | | | | | | +------------------- LC56 en_io
        | | | | | | | +----------------- LC64 enld
        | | | | | | | | +--------------- LC50 |jie:101|~38~1
        | | | | | | | | | +------------- LC62 |jie:101|7474:40|1Q
        | | | | | | | | | | +----------- LC57 |jie:101|7474:41|1Q
        | | | | | | | | | | | +--------- LC58 |jie:101|74175:42|4Q
        | | | | | | | | | | | | +------- LC63 |jie:101|74175:42|3Q
        | | | | | | | | | | | | | +----- LC55 |jie:101|74175:42|2Q
        | | | | | | | | | | | | | | +--- LC60 T3
        | | | | | | | | | | | | | | | +- LC59 t4
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC49 -> * * * - * * * * - - - - - - - - | - * * * | <-- a0
LC51 -> * * * * * * * * - - - - - - - - | - * * * | <-- a1
LC53 -> * * * * * * * * - - - - - - - - | - * * * | <-- a2
LC52 -> * * * * * * * * - - - - - - - - | - * * * | <-- a3
LC54 -> * * * * * * * * - - - - - - - - | - * * * | <-- a4
LC50 -> - - - - - - - - * - * - - - - - | - - - * | <-- |jie:101|~38~1
LC62 -> - - - - - - - - - - - * * * - - | - - - * | <-- |jie:101|7474:40|1Q
LC57 -> * * * * * * * * * - - - - - * * | - * * * | <-- |jie:101|7474:41|1Q
LC58 -> - * * * * - - - - - * - * - * * | - - - * | <-- |jie:101|74175:42|4Q
LC63 -> * * * * * * * * - - - - - * - * | - * * * | <-- |jie:101|74175:42|3Q
LC55 -> * * * * * * * * - * - - - - - - | - * * * | <-- |jie:101|74175:42|2Q

Pin
1    -> - - - - - - - - - - - - - - - - | - - - - | <-- CLR
12   -> - - - - - - - - * - - - - - - - | - - - * | <-- DP
10   -> - - - - - - - - - * - * * * - - | - - - * | <-- H
9    -> - - - - - - - - - - * * * * - - | - - - * | <-- TJ
13   -> - * - - - - - - - - - - - - - - | - - - * | <-- z
LC31 -> - - - - - - - - * - * - - - - - | - - - * | <-- |jie:101|~37~1
LC33 -> - * * * * - - - - - - - - - - - | - - - * | <-- P1
LC47 -> - * - - - - - - - - - - - - - - | - - - * | <-- |74273:41|Q8
LC39 -> - - * - - - - - - - - - - - - - | - - - * | <-- |74273:41|Q7
LC42 -> - - - * - - - - - - - - - - - - | - - - * | <-- |74273:41|Q6
LC34 -> - - - - * - - - - - - - - - - - | - - - * | <-- |74273:41|Q5


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:               e:\cpu_design\cpumodel\kong_sim.rpt
kong_sim

** EQUATIONS **

CLR      : INPUT;
DP       : INPUT;
H        : INPUT;
IR4      : INPUT;
IR5      : INPUT;
IR6      : INPUT;
IR7      : INPUT;
QD       : INPUT;
TJ       : INPUT;
z        : INPUT;

-- Node name is 'alu_bus' = '|74273:38|Q3' 
-- Equation name is 'alu_bus', type is output 
 alu_bus = DFFE( _EQ001 $  VCC,  _EQ002, GLOBAL( CLR),  VCC,  VCC);
  _EQ001 =  a0 &  a1 & !a3 &  a4
         #  a2 & !a3 &  a4;
  _EQ002 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'a0' = '|7474:56|1Q' 
-- Equation name is 'a0', type is output 
 a0      = DFFE( _EQ003 $  _EQ004,  _EQ005, GLOBAL( CLR), !_EQ006,  VCC);
  _EQ003 =  a0 &  a1 &  a3 &  _X001 &  _X002 &  _X003 &  _X004 &  _X005 & !z
         #  a0 &  a1 & !a2 &  a3 &  _X001 &  _X002 &  _X003 &  _X004 &  _X005;
  _X001  = EXP(!a0 & !a1 & !a2 &  a3);
  _X002  = EXP( a0 & !a1 & !a2 & !a3);
  _X003  = EXP(!a0 & !a1 & !a2 &  a4);
  _X004  = EXP( a1 & !a3 & !a4);
  _X005  = EXP( a2 & !a4);
  _EQ004 =  _X001 &  _X002 &  _X003 &  _X004 &  _X005;
  _X001  = EXP(!a0 & !a1 & !a2 &  a3);
  _X002  = EXP( a0 & !a1 & !a2 & !a3);
  _X003  = EXP(!a0 & !a1 & !a2 &  a4);
  _X004  = EXP( a1 & !a3 & !a4);
  _X005  = EXP( a2 & !a4);
  _EQ005 = !_LC055 &  _LC057 &  _LC063;
  _EQ006 =  _LC047 &  _LC057 & !_LC058 &  P1;

-- Node name is 'a1' = '|7474:57|2Q' 
-- Equation name is 'a1', type is output 
 a1      = DFFE( _EQ007 $  GND,  _EQ008, GLOBAL( CLR), !_EQ009,  VCC);
  _EQ007 =  a0 &  a1 & !a2 &  a3 &  a4
         # !a0 &  a1 & !a2 & !a3 &  a4
         #  a0 & !a1 & !a2 & !a3;
  _EQ008 = !_LC055 &  _LC057 &  _LC063;
  _EQ009 =  _LC039 &  _LC057 & !_LC058 &  P1;

-- Node name is 'a2' = '|7474:57|1Q' 
-- Equation name is 'a2', type is output 
 a2      = DFFE( _EQ010 $  GND,  _EQ011, GLOBAL( CLR), !_EQ012,  VCC);
  _EQ010 = !a1 & !a2 &  a3 &  a4;
  _EQ011 = !_LC055 &  _LC057 &  _LC063;
  _EQ012 =  _LC042 &  _LC057 & !_LC058 &  P1;

-- Node name is 'a3' = '|7474:58|2Q' 
-- Equation name is 'a3', type is output 
 a3      = DFFE( _EQ013 $  _EQ014,  _EQ015, GLOBAL( CLR), !_EQ016,  VCC);
  _EQ013 =  a0 &  a1 & !a3 &  a4 &  _X006 &  _X007
         # !a0 & !a1 & !a3 &  a4 &  _X006 &  _X007;
  _X006  = EXP(!a1 &  a2);
  _X007  = EXP(!a0 &  a2);
  _EQ014 =  a4 &  _X006 &  _X007;
  _X006  = EXP(!a1 &  a2);
  _X007  = EXP(!a0 &  a2);
  _EQ015 = !_LC055 &  _LC057 &  _LC063;
  _EQ016 =  _LC034 &  _LC057 & !_LC058 &  P1;

-- Node name is 'a4' = '|7474:58|1Q' 
-- Equation name is 'a4', type is output 
 a4      = DFFE( _EQ017 $  GND,  _EQ018, GLOBAL( CLR),  VCC,  VCC);
  _EQ017 =  a0 &  a1 &  a2 &  a3 &  a4
         # !a1 & !a2 &  a3 &  a4
         #  a0 & !a1 & !a2 &  a4
         # !a0 &  a1 & !a2 & !a3;
  _EQ018 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'en' 
-- Equation name is 'en', location is LC029, type is output.
 en      = LCELL( _EQ019 $  GND);
  _EQ019 =  a0 &  a1 &  a2 &  a3 &  a4;

-- Node name is 'en_io' = '|74273:39|Q3' 
-- Equation name is 'en_io', type is output 
 en_io   = DFFE( _EQ020 $  GND,  _EQ021, GLOBAL( CLR),  VCC,  VCC);
  _EQ020 = !a0 &  a1 &  a2 &  a3 &  a4;
  _EQ021 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'enld' = '|74273:38|Q1' 
-- Equation name is 'enld', type is output 
 enld    = DFFE( _EQ022 $  GND,  _EQ023, GLOBAL( CLR),  VCC,  VCC);
  _EQ022 =  a0 & !a1 & !a2 &  a3 & !a4
         #  a0 &  a1 & !a3 &  a4
         #  a2 & !a3 &  a4;
  _EQ023 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'ldar' = '|74273:40|Q6' 
-- Equation name is 'ldar', type is output 
 ldar    = DFFE( _EQ024 $  GND,  _EQ025, GLOBAL( CLR),  VCC,  VCC);
  _EQ024 =  a0 & !a2 &  a3 &  a4
         # !a0 &  a1 & !a2 &  a4
         #  a0 & !a1 & !a2 & !a3;
  _EQ025 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'lddr' = '|74273:39|Q4' 
-- Equation name is 'lddr', type is output 
 lddr    = DFFE( _EQ026 $  GND,  _EQ027, GLOBAL( CLR),  VCC,  VCC);
  _EQ026 = !a0 &  a1 & !a2 & !a3 & !a4;
  _EQ027 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'lddr1' = '|74273:38|Q7' 
-- Equation name is 'lddr1', type is output 
 lddr1   = DFFE( _EQ028 $  GND,  _EQ029, GLOBAL( CLR),  VCC,  VCC);
  _EQ028 =  a0 &  a1 & !a3 &  a4
         #  a2 & !a3 &  a4;
  _EQ029 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'lddr2' = '|74273:38|Q8' 
-- Equation name is 'lddr2', type is output 
 lddr2   = DFFE( _EQ030 $  GND,  _EQ031, GLOBAL( CLR),  VCC,  VCC);
  _EQ030 =  a0 &  a1 & !a3 &  a4
         #  a2 & !a3 &  a4;
  _EQ031 = !_LC055 &  _LC057 &  _LC063;

-- Node name is 'ldir' = '|74273:39|Q5'