cpurom.vhl

来自「简单的CPU设计数字系统实验」· VHL 代码 · 共 53 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY cpu_rom IS
	
	PORT(
		a4,a3,a2,a1,a0	: IN	STD_LOGIC;
		
        sw_pc,pc_ar,pc_in,ram_ir_or,m_ri,ri_m,plus,sub,and	:  OUT	STD_LOGIC;
        or,mul,m_pc,en_io	:  OUT	STD_LOGIC);

    END cpu_rom;

ARCHITECTURE a OF cpu_rom IS
	SIGNAL sk : STD_LOGIC_VECTOR(4 downto 0);
	SIGNAL sel : STD_LOGIC_VECTOR(12 downto 0);
BEGIN
	
   sk<=a4&a3&a2&a1&a0;
sel<="100000000000000001"when sk="00000" else
     "011000000000000001"when sk="00001" else
     "000100000000010000"when sk="00010" else
     "011000000000001010"when sk="11010" else
     "000010000000000001"when sk="01010" else
     "011001000000001011"when sk="11011" else
     "000010000000000001"when sk="01011" else  
     "000000100000000001"when sk="11100" else
     "000000010000000001"when sk="11101" else
     "000000001000000001"when sk="11110" else
     "000000000100000001"when sk="11111" else
     "000000000010000001"when sk="01111" else
     "011000000000001100"when sk="11001" else
     "000000000001000001"when sk="01100" else
     "001000000000000001"when sk="01101" else
     "000000000000100001"when sk="01001" else

   
     "000000000000000000";
     


sw_pc<=sel(12);pc_ar<=sel(11);
pc_in<=sel(10);ram_ir_dr<=sel(9);m_ri<=sel(8);ri_m<=sel(7);
lus<=sel(6);sub<=sel(5);and<=sel(4);or<=sel(3);
mul<=sel(2);m_pc<=sel(1);en_io<=sel(0);	



END a;