alu_reg.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 722 行 · 第 1/5 页
RPT
722 行
- 7 - A 14 OR2 s ! 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~271~1
- 8 - A 14 OR2 s ! 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~271~2
- 2 - A 14 OR2 ! 0 4 0 4 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|:271
- 5 - A 11 AND2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~272~1
- 6 - A 11 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~272~2
- 7 - A 11 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|:272
- 4 - A 09 AND2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~273~1
- 5 - A 09 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~273~2
- 6 - A 09 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|:273
- 5 - F 10 AND2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~274~1
- 3 - F 14 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|~274~2
- 6 - F 10 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|:274
- 1 - F 14 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|:275
- 6 - F 14 OR2 0 4 0 8 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder0|:276
- 1 - A 20 OR2 0 4 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:111
- 8 - A 04 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~128~1
- 3 - A 04 OR2 0 3 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:128
- 1 - A 11 OR2 s 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~129~1
- 5 - A 04 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~130~1
- 3 - A 09 OR2 0 3 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:130
- 3 - F 10 OR2 0 3 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:131
- 1 - F 21 OR2 0 3 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:132
- 6 - F 17 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:134
- 8 - F 17 OR2 0 4 0 4 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:135
- 6 - F 03 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:143
- 3 - F 01 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:147
- 2 - F 21 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:148
- 8 - F 20 AND2 0 3 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:149
- 6 - A 01 AND2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~272~1
- 7 - A 01 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~272~2
- 8 - A 01 OR2 0 4 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:272
- 4 - A 05 AND2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~273~1
- 5 - A 05 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~273~2
- 3 - A 05 OR2 0 3 0 4 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:273
- 1 - A 04 AND2 s ! 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~274~1
- 2 - A 04 OR2 s ! 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~274~2
- 7 - A 08 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:274
- 5 - F 01 OR2 s 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~275~1
- 4 - F 01 OR2 0 4 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:275
- 8 - F 21 OR2 s 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~276~1
- 3 - F 21 OR2 ! 0 4 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:276
- 1 - F 17 OR2 s 0 3 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|~277~1
- 5 - F 21 OR2 0 4 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:277
- 6 - F 23 OR2 0 4 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:278
- 4 - F 21 OR2 0 4 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder1|:279
- 5 - A 08 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:115
- 1 - F 01 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:116
- 1 - F 22 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:117
- 4 - F 19 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:118
- 5 - F 23 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:119
- 5 - F 14 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:120
- 2 - A 05 OR2 0 4 0 4 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:130
- 7 - F 01 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:147
- 5 - F 22 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:148
- 6 - F 22 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:149
- 4 - F 23 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:150
- 4 - F 14 AND2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:151
- 6 - A 08 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:274
- 2 - A 24 OR2 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry6
- 5 - A 02 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry7
- 1 - A 02 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry8
- 8 - A 07 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry9
- 8 - F 09 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry10
- 6 - F 18 OR2 0 4 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry11
- 1 - F 18 OR2 0 3 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry12
- 8 - A 22 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~1
- 1 - A 22 AND2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~2
- 2 - A 02 OR2 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:221
- 5 - A 07 OR2 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:222
- 2 - F 09 OR2 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:223
- 3 - F 18 OR2 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:224
- 8 - F 18 OR2 0 3 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:225
- 1 - F 16 OR2 0 3 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:226
- 7 - F 14 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~1
- 4 - F 13 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~2
- 7 - F 13 OR2 s 0 3 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~3
- 6 - F 13 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~4
- 5 - F 16 OR2 s 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~5
- 6 - F 16 OR2 0 4 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:227
- 3 - A 22 AND2 0 2 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|decoder_node1_1
- 1 - A 13 AND2 0 2 0 1 |alu:142|LPM_MULT:4|multcore:mult_core|decoder_node2_0
- 8 - F 14 AND2 0 2 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|decoder_node2_6
- 4 - A 06 AND2 0 2 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|decoder_node3_3
- 6 - F 21 AND2 0 2 0 6 |alu:142|LPM_MULT:4|multcore:mult_core|decoder_node3_7
- 7 - F 21 AND2 0 2 0 3 |alu:142|LPM_MULT:4|multcore:mult_core|decoder_node5_5
- 4 - F 24 AND2 0 2 0 2 |alu:142|LPM_MULT:4|multcore:mult_core|decoder_node5_6
- 3 - A 12 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:112|:46
- 7 - A 12 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:112|:51
- 2 - A 07 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:130|:46
- 7 - A 07 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:130|:51
- 1 - F 09 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:148|:46
- 7 - F 09 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:148|:51
- 3 - F 11 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:166|:46
- 8 - F 11 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:166|:51
- 4 - F 07 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:184|:46
- 8 - F 07 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:184|:51
- 1 - F 02 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:202|:46
- 6 - F 02 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:202|:51
- 4 - F 16 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:220|:46
- 7 - F 16 OR2 2 2 0 1 |alu:142|LPM_MUX:3|muxlut:220|:51
- 6 - A 12 OR2 1 3 0 1 |alu:142|LPM_MUX:49|muxlut:92|result_node
- 6 - A 07 OR2 1 3 0 1 |alu:142|LPM_MUX:49|muxlut:107|result_node
- 5 - F 09 OR2 1 2 0 1 |alu:142|LPM_MUX:49|muxlut:122|result_node
- 7 - F 11 OR2 1 2 0 1 |alu:142|LPM_MUX:49|muxlut:137|result_node
- 7 - F 07 OR2 1 2 0 1 |alu:142|LPM_MUX:49|muxlut:152|result_node
- 5 - F 02 OR2 1 2 0 1 |alu:142|LPM_MUX:49|muxlut:167|result_node
- 5 - F 08 OR2 1 2 0 1 |alu:142|LPM_MUX:49|muxlut:182|result_node
- 7 - F 08 OR2 1 3 0 1 |alu:142|MUX:52|lpm_mux:31|muxlut:42|:39
- 6 - F 08 OR2 1 3 0 1 |alu:142|MUX:52|lpm_mux:31|muxlut:42|:40
- 2 - F 08 OR2 2 2 1 0 |alu:142|cout (|alu:142|:58)
- 2 - E 17 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_0
- 8 - E 20 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_1
- 2 - E 23 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_2
- 5 - E 23 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_3
- 1 - E 02 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_4
- 1 - E 16 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_5
- 1 - E 07 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_6
- 2 - E 12 DFFE + 1 2 0 2 |LPM_MUX:62|altshift:external_latency_ffs|points0_7
- 1 - E 17 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:94|~46~1
- 3 - E 17 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:94|~51~1
- 2 - E 20 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:112|~46~1
- 3 - E 20 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:112|~51~1
- 3 - E 23 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:130|~46~1
- 6 - E 23 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:130|~51~1
- 1 - E 24 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:148|~46~1
- 7 - E 23 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:148|~51~1
- 7 - E 15 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:166|~46~1
- 8 - E 19 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:166|~51~1
- 3 - E 16 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:184|~46~1
- 4 - E 16 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:184|~51~1
- 4 - E 07 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:202|~46~1
- 5 - E 07 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:202|~51~1
- 5 - E 12 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:220|~46~1
- 3 - E 12 OR2 s 1 2 0 1 |LPM_MUX:62|muxlut:220|~51~1
- 6 - E 17 DFFE + 1 2 0 1 |LPM_MUX:63|altshift:external_latency_ffs|points0_0
- 6 - E 20 DFFE + 1 2 0 1 |LPM_MUX:63|altshift:external_latency_ffs|points0_1
- 2 - E 21 DFFE + 1 2 0 1 |LPM_MUX:63|altshift:external_latency_ffs|points0_2
- 8 - E 24 DFFE + 1 2 0 1 |LPM_MUX:63|altshift:external_latency_ffs|points0_3
- 2 - E 22 DFFE + 1 2 0 1 |LPM_MUX:63|altshift:external_latency_ffs|points0_4
- 8 - E 16 DFFE + 1 2 0 1 |LPM_MUX:63|altshift:external_latency_ffs|points0_5
- 2 - E 07 DFFE + 1 2 0 1 |LPM_MUX:63|altshift:external_latency_ffs|points0_6
- 1 - E 12 DFFE + 1 2 0 ⌨️ 快捷键说明
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