alu_reg.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 722 行 · 第 1/5 页
RPT
722 行
E22 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 4/22( 18%)
E23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 11/22( 50%)
E24 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 11/22( 50%)
F1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
F2 6/ 8( 75%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
F3 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
F7 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
F8 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
F9 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
F10 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
F11 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
F13 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F14 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 8/22( 36%)
F15 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F16 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
F17 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
F18 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
F19 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
F20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F21 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 7/22( 31%)
F22 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
F23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
F24 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 37/96 ( 38%)
Total logic cells used: 346/1152 ( 30%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.10/4 ( 77%)
Total fan-in: 1074/4608 ( 23%)
Total input pins required: 26
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 346
Total flipflops required: 64
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 91/1152 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 0 8 8 1 8 8 8 0 8 8 0 1 8 0 0 1 0 0 1 0 8 0 8 100/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 2 1 1 0 8 8 7 0 2 1 0 7 0 8 1 8 7 7 7 8 7 2 2 8 8 110/0
F: 8 6 8 0 0 0 8 7 8 8 8 0 0 8 8 7 7 8 8 8 1 8 3 8 1 136/0
Total: 18 15 9 8 16 9 23 15 18 9 16 15 0 17 17 15 14 16 15 16 9 10 13 16 17 346/0
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alu_reg.rpt
alu_reg
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT 0 0 0 9 ALU_BUS
8 - - A -- BIDIR 0 1 0 4 D0
144 - - A -- BIDIR 0 1 0 4 D1
101 - - A -- BIDIR 0 1 0 4 D2
33 - - F -- BIDIR 0 1 0 4 D3
32 - - F -- BIDIR 0 1 0 4 D4
81 - - F -- BIDIR 0 1 0 4 D5
79 - - F -- BIDIR 0 1 0 4 D6
31 - - F -- BIDIR 0 1 0 4 D7
114 - - - 04 INPUT 0 0 0 1 in0
113 - - - 03 INPUT 0 0 0 1 in1
72 - - - 03 INPUT 0 0 0 1 in2
73 - - - 01 INPUT 0 0 0 1 in3
30 - - F -- INPUT 0 0 0 1 in4
118 - - - 06 INPUT 0 0 0 1 in5
65 - - - 09 INPUT 0 0 0 1 in6
119 - - - 07 INPUT 0 0 0 1 in7
69 - - - 06 INPUT 0 0 0 1 LDDR1
51 - - - 14 INPUT 0 0 0 1 LDDR2
138 - - - 21 INPUT 0 0 0 1 LDR0
86 - - E -- INPUT 0 0 0 1 LDR1
132 - - - 16 INPUT 0 0 0 1 LDR2
47 - - - 16 INPUT 0 0 0 1 LDR3
121 - - - 10 INPUT 0 0 0 9 r_bus
54 - - - -- INPUT 0 0 0 16 sa0
83 - - E -- INPUT 0 0 0 8 sa1
56 - - - -- INPUT 0 0 0 16 sb0
124 - - - -- INPUT 0 0 0 8 sb1
68 - - - 07 INPUT 0 0 0 9 SW_BUS
63 - - - 10 INPUT 0 0 0 16 s0
125 - - - -- INPUT 0 0 0 16 s1
59 - - - 12 INPUT 0 0 0 9 s2
55 - - - -- INPUT G 0 0 0 2 t1
131 - - - 16 INPUT 0 0 0 4 t3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alu_reg.rpt
alu_reg
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - F -- OUTPUT 0 1 0 0 CN4
8 - - A -- TRI 0 1 0 4 D0
144 - - A -- TRI 0 1 0 4 D1
101 - - A -- TRI 0 1 0 4 D2
33 - - F -- TRI 0 1 0 4 D3
32 - - F -- TRI 0 1 0 4 D4
81 - - F -- TRI 0 1 0 4 D5
79 - - F -- TRI 0 1 0 4 D6
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