alu_reg.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 722 行 · 第 1/5 页
RPT
722 行
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alu_reg.rpt
alu_reg
***** Logic for device 'alu_reg' compiled without errors.
Device: EPF10K20TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R
E E E E E E E E E E A E E E E E E E E
S S S S S S S S S S G L V S S S S S S S S
E E E E G E E E V E E G E N U C E r E E E V E E E E
R R R R N L R R R C R L R N R D _ C R _ R R R C R R R R
V V V V D D V V V C V D V D V I B s I V b V i i V V C i i V V V V
D E E E E I R E E E I E R t E I E N U s b N E u E n n E E I n n E E E E
1 D D D D O 0 D D D O D 2 3 D O D T S 1 1 T D s D 7 5 D D O 0 1 D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | RESERVED
D0 | 8 101 | D2
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
RESERVED | 11 98 | RESERVED
RESERVED | 12 97 | RESERVED
RESERVED | 13 96 | RESERVED
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K20TC144-3 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | r0_1
RESERVED | 23 86 | LDR1
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
r0_6 | 26 83 | sa1
r0_5 | 27 82 | r0_7
r0_3 | 28 81 | D5
r0_2 | 29 80 | CN4
in4 | 30 79 | D6
D7 | 31 78 | RESERVED
D4 | 32 77 | ^MSEL0
D3 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | in3
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R r R R V R L R r G L V V s t s G G s R V R s R i G R S L R V i
E E E N E 0 E E C E D E 0 N D C C a 1 b N N 2 E C E 0 E n N E W D E C n
S S S D S _ S S C S R S _ D D C C 0 0 D D S C S S 6 D S _ D S C 2
E E E I E 4 E E I E 3 E 0 I R I I I I E I E E I E B R E I
R R R O R R R O R R O 2 N N N N R O R R O R U 1 R O
V V V V V V V V T T T T V V V V S V
E E E E E E E E E E E E E
D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\maxplus2\cpu_design\cpu_model\alu_reg.rpt
alu_reg
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
A2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
A4 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 12/22( 54%)
A5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A7 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
A8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
A9 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
A11 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
A12 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
A13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
A20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
A22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
A24 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
E1 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 3/22( 13%)
E2 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
E3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
E5 8/ 8(100%) 7/ 8( 87%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
E6 8/ 8(100%) 8/ 8(100%) 0/ 8( 0%) 0/2 0/2 17/22( 77%)
E7 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 9/22( 40%)
E9 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 3/22( 13%)
E10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
E12 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 9/22( 40%)
E13 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 2/2 0/2 7/22( 31%)
E14 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
E15 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 7/22( 31%)
E16 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 0/2 9/22( 40%)
E17 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 9/22( 40%)
E18 7/ 8( 87%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 8/22( 36%)
E19 8/ 8(100%) 1/ 8( 12%) 6/ 8( 75%) 2/2 0/2 8/22( 36%)
E20 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 9/22( 40%)
E21 2/ 8( 25%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 4/22( 18%)
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