alu.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 891 行 · 第 1/5 页
RPT
891 行
- 3 - E 04 OR2 4 0 0 3 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:118
- 4 - E 09 OR2 4 0 0 3 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:119
- 6 - E 04 OR2 4 0 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:120
- 7 - D 18 OR2 4 0 0 4 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:130
- 2 - D 18 AND2 4 0 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:147
- 2 - E 01 AND2 4 0 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:148
- 6 - D 22 AND2 4 0 0 3 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:149
- 3 - E 09 AND2 4 0 0 3 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:150
- 8 - E 04 AND2 4 0 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:151
- 3 - D 09 OR2 4 0 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|csa_cell:adder2|:274
- 2 - D 24 OR2 0 4 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry6
- 2 - D 23 OR2 0 3 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry7
- 3 - D 21 OR2 0 3 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry8
- 2 - D 17 OR2 0 3 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry9
- 2 - D 13 OR2 0 3 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry10
- 1 - E 21 OR2 0 3 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry11
- 2 - E 24 OR2 0 3 0 2 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry12
- 1 - E 16 OR2 0 3 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry13
- 1 - D 14 OR2 s 4 0 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~1
- 2 - D 14 AND2 s 2 2 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~2
- 4 - D 24 OR2 s 0 4 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~139~3
- 5 - E 12 OR2 s 0 4 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~1
- 4 - E 05 OR2 s 4 0 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~2
- 5 - E 05 OR2 s 0 4 0 1 |LPM_MULT:4|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|~227~3
- 5 - E 04 AND2 2 0 0 6 |LPM_MULT:4|multcore:mult_core|decoder_node0_7
- 7 - D 02 AND2 2 0 0 1 |LPM_MULT:4|multcore:mult_core|decoder_node1_6
- 5 - D 02 AND2 2 0 0 1 |LPM_MULT:4|multcore:mult_core|decoder_node1_7
- 3 - D 19 AND2 2 0 0 3 |LPM_MULT:4|multcore:mult_core|decoder_node3_3
- 7 - D 20 AND2 2 0 0 1 |LPM_MULT:4|multcore:mult_core|decoder_node4_1
- 1 - E 02 AND2 2 0 0 1 |LPM_MULT:4|multcore:mult_core|decoder_node4_7
- 4 - D 14 AND2 2 0 0 3 |LPM_MULT:4|multcore:mult_core|decoder_node5_0
- 8 - E 02 AND2 2 0 0 2 |LPM_MULT:4|multcore:mult_core|decoder_node5_6
- 2 - E 16 OR2 4 0 1 0 |LPM_MUX:3|muxlut:94|result_node
- 7 - D 21 OR2 1 3 1 0 |LPM_MUX:3|muxlut:112|result_node
- 2 - D 21 OR2 s 3 0 0 1 |LPM_MUX:3|muxlut:112|~46~1
- 4 - D 21 OR2 1 3 0 1 |LPM_MUX:3|muxlut:112|:47
- 8 - D 21 OR2 2 2 0 1 |LPM_MUX:3|muxlut:112|:50
- 5 - D 17 OR2 1 3 1 0 |LPM_MUX:3|muxlut:130|result_node
- 8 - D 17 OR2 s 3 0 0 1 |LPM_MUX:3|muxlut:130|~46~1
- 4 - D 17 OR2 1 3 0 1 |LPM_MUX:3|muxlut:130|:47
- 7 - D 17 OR2 2 2 0 1 |LPM_MUX:3|muxlut:130|:50
- 3 - D 13 OR2 1 3 1 0 |LPM_MUX:3|muxlut:148|result_node
- 4 - D 13 OR2 s 3 0 0 1 |LPM_MUX:3|muxlut:148|~46~1
- 5 - D 13 OR2 1 3 0 1 |LPM_MUX:3|muxlut:148|:47
- 8 - D 13 OR2 2 2 0 1 |LPM_MUX:3|muxlut:148|:50
- 8 - E 21 OR2 1 3 1 0 |LPM_MUX:3|muxlut:166|result_node
- 3 - E 21 OR2 s 3 0 0 1 |LPM_MUX:3|muxlut:166|~46~1
- 4 - E 21 OR2 1 3 0 1 |LPM_MUX:3|muxlut:166|:47
- 7 - E 21 OR2 2 2 0 1 |LPM_MUX:3|muxlut:166|:50
- 1 - E 24 OR2 1 3 1 0 |LPM_MUX:3|muxlut:184|result_node
- 4 - E 24 OR2 s 3 0 0 1 |LPM_MUX:3|muxlut:184|~46~1
- 5 - E 24 OR2 1 3 0 1 |LPM_MUX:3|muxlut:184|:47
- 8 - E 24 OR2 2 2 0 1 |LPM_MUX:3|muxlut:184|:50
- 5 - E 16 OR2 1 3 1 0 |LPM_MUX:3|muxlut:202|result_node
- 3 - E 16 OR2 s 3 0 0 1 |LPM_MUX:3|muxlut:202|~46~1
- 4 - E 16 OR2 1 3 0 1 |LPM_MUX:3|muxlut:202|:47
- 8 - E 16 OR2 2 2 0 1 |LPM_MUX:3|muxlut:202|:50
- 2 - E 05 OR2 1 3 1 0 |LPM_MUX:3|muxlut:220|result_node
- 1 - E 05 OR2 s 3 0 0 1 |LPM_MUX:3|muxlut:220|~46~1
- 7 - E 05 OR2 1 3 0 1 |LPM_MUX:3|muxlut:220|:47
- 6 - E 15 OR2 2 2 0 1 |LPM_MUX:3|muxlut:220|:50
- 8 - E 15 OR2 2 2 0 1 |MUX:52|lpm_mux:31|muxlut:42|:39
- 3 - E 15 OR2 3 1 0 1 |MUX:52|lpm_mux:31|muxlut:42|:40
- 5 - E 15 OR2 2 2 1 0 :58
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\cpu_design\cpumodel\alu.rpt
alu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 29/ 96( 30%) 10/ 48( 20%) 32/ 48( 66%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 28/ 96( 29%) 25/ 48( 52%) 13/ 48( 27%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cpu_design\cpumodel\alu.rpt
alu
** EQUATIONS **
a0_0 : INPUT;
a0_1 : INPUT;
a0_2 : INPUT;
a0_3 : INPUT;
a0_4 : INPUT;
a0_5 : INPUT;
a0_6 : INPUT;
a0_7 : INPUT;
a1_0 : INPUT;
a1_1 : INPUT;
a1_2 : INPUT;
a1_3 : INPUT;
a1_4 : INPUT;
a1_5 : INPUT;
a1_6 : INPUT;
a1_7 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC5_E15;
-- Node name is 'result0'
-- Equation name is 'result0', type is output
result0 = _LC2_E16;
-- Node name is 'result1'
-- Equation name is 'result1', type is output
result1 = _LC7_D21;
-- Node name is 'result2'
-- Equation name is 'result2', type is output
result2 = _LC5_D17;
-- Node name is 'result3'
-- Equation name is 'result3', type is output
result3 = _LC3_D13;
-- Node name is 'result4'
-- Equation name is 'result4', type is output
result4 = _LC8_E21;
-- Node name is 'result5'
-- Equation name is 'result5', type is output
result5 = _LC1_E24;
-- Node name is 'result6'
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