alu.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 891 行 · 第 1/5 页
RPT
891 行
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
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R R R G R R R R V R s R R G R V V a a a G G a R V a R a R G R R a R V R
E E E N E E E E C E e E E N E C C 1 0 1 N N 1 E C 1 E 0 E N E E 1 E C E
S S S D S S S S C S l S S D S C C _ _ _ D D _ S C _ S _ S D S S _ S C S
E E E I E E E E I E 1 E E I E I I 3 2 4 I I 1 E I 0 E 7 E I E E 2 E I E
R R R O R R R R O R R R O R N N N N R O R R O R R R O R
V V V V V V V V V V V T T T T V V V V V V V
E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\cpu_design\cpumodel\alu.rpt
alu
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
D2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
D6 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
D8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
D9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
D10 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
D13 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
D14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
D15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
D16 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
D17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
D18 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
D19 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
D20 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/22( 50%)
D21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
D22 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
D23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
D24 5/ 8( 62%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
E1 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
E2 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 5/22( 22%)
E3 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
E4 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
E5 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
E7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
E9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
E11 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
E12 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
E15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
E16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
E21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
E22 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
E24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 12/22( 54%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 22/96 ( 22%)
Total logic cells used: 229/1152 ( 19%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.58/4 ( 89%)
Total fan-in: 820/4608 ( 17%)
Total input pins required: 19
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 229
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 58/1152 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 8 0 0 0 8 0 8 8 8 0 0 0 8 8 8 6 8 8 7 8 8 8 8 5 130/0
E: 8 8 8 8 7 0 8 0 8 0 2 8 0 0 0 8 8 0 0 0 0 8 2 0 8 99/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 16 8 8 7 8 8 8 16 8 2 8 0 8 8 16 14 8 8 7 8 16 10 8 13 229/0
Device-Specific Information: e:\cpu_design\cpumodel\alu.rpt
alu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
140 - - - 22 INPUT 0 0 0 18 a0_0
88 - - D -- INPUT 0 0 0 21 a0_1
55 - - - -- INPUT 0 0 0 25 a0_2
113 - - - 03 INPUT 0 0 0 26 a0_3
126 - - - -- INPUT 0 0 0 23 a0_4
125 - - - -- INPUT 0 0 0 23 a0_5
110 - - - 01 INPUT 0 0 0 22 a0_6
64 - - - 09 INPUT 0 0 0 20 a0_7
62 - - - 11 INPUT 0 0 0 21 a1_0
59 - - - 12 INPUT 0 0 0 28 a1_1
69 - - - 06 INPUT 0 0 0 24 a1_2
54 - - - -- INPUT 0 0 0 25 a1_3
56 - - - -- INPUT 0 0 0 26 a1_4
124 - - - -- INPUT 0 0 0 21 a1_5
119 - - - 07 INPUT 0 0 0 22 a1_6
118 - - - 06 INPUT 0 0 0 17 a1_7
36 - - - 24 INPUT 0 0 0 23 sel0
47 - - - 16 INPUT 0 0 0 9 sel1
141 - - - 23 INPUT 0 0 0 9 sel2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cpu_design\cpumodel\alu.rpt
alu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - E -- OUTPUT 0 1 0 0 cout
27 - - E -- OUTPUT 0 1 0 0 result0
23 - - D -- OUTPUT 0 1 0 0 result1
21 - - D -- OUTPUT 0 1 0 0 result2
19 - - D -- OUTPUT 0 1 0 0 result3
29 - - E -- OUTPUT 0 1 0 0 result4
26 - - E -- OUTPUT 0 1 0 0 result5
83 - - E -- OUTPUT 0 1 0 0 result6
87 - - E -- OUTPUT 0 1 0 0 result7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
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