jiepai.rpt
来自「简单的CPU设计数字系统实验」· RPT 代码 · 共 604 行 · 第 1/2 页
RPT
604 行
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jiepai.rpt
jiepai
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 20 AND2 0 2 1 0 :1
- 4 - C 16 AND2 0 3 1 0 :2
- 5 - C 16 AND2 0 3 1 0 :3
- 2 - C 13 AND2 0 2 1 0 :4
- 7 - C 16 OR2 1 1 0 3 :24
- 4 - C 13 OR2 s 2 1 0 1 ~35~1
- 5 - C 13 OR2 ! 0 2 0 1 :36
- 1 - C 13 AND2 ! 1 0 0 2 :37
- 6 - C 16 OR2 2 1 0 3 :51
- 3 - C 13 DFFE 1 3 1 5 |7474:32|1Q (|7474:32|:9)
- 3 - C 16 DFFE 1 1 0 2 |7474:46|1Q (|7474:46|:9)
- 1 - C 16 DFFE 0 2 0 4 |74175:17|4Q (|74175:17|:13)
- 8 - C 16 DFFE 0 3 0 3 |74175:17|3Q (|74175:17|:14)
- 2 - C 16 DFFE 0 3 0 3 |74175:17|2Q (|74175:17|:15)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jiepai.rpt
jiepai
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 1/ 96( 1%) 0/ 48( 0%) 1/ 48( 2%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jiepai.rpt
jiepai
** CLOCK SIGNALS **
Type Fan-out Name
DFF 4 |74175:17|4Q
INPUT 3 H
LCELL 3 :24
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jiepai.rpt
jiepai
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 TJ
LCELL 3 :51
Device-Specific Information: d:\maxplus2\cpu_design\cpu_module\jiepai.rpt
jiepai
** EQUATIONS **
DP : INPUT;
GD : INPUT;
H : INPUT;
TJ : INPUT;
-- Node name is 'start'
-- Equation name is 'start', type is output
start = _LC3_C13;
-- Node name is 'T1'
-- Equation name is 'T1', type is output
T1 = _LC4_C16;
-- Node name is 'T2'
-- Equation name is 'T2', type is output
T2 = _LC5_C16;
-- Node name is 'T3'
-- Equation name is 'T3', type is output
T3 = _LC2_C13;
-- Node name is 'T4'
-- Equation name is 'T4', type is output
T4 = _LC2_C20;
-- Node name is '|7474:32|:9' = '|7474:32|1Q'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = DFFE( _EQ001, _LC1_C16, !TJ, VCC, VCC);
_EQ001 = _LC1_C13 & _LC5_C13;
-- Node name is '|7474:46|:9' = '|7474:46|1Q'
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = DFFE( _LC2_C16, !H, VCC, VCC, VCC);
-- Node name is '|74175:17|:15' = '|74175:17|2Q'
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = DFFE( _LC8_C16, _LC7_C16, _LC6_C16, VCC, VCC);
-- Node name is '|74175:17|:14' = '|74175:17|3Q'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = DFFE( _LC1_C16, _LC7_C16, _LC6_C16, VCC, VCC);
-- Node name is '|74175:17|:13' = '|74175:17|4Q'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = DFFE( VCC, _LC7_C16, _LC6_C16, VCC, VCC);
-- Node name is ':1'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = LCELL( _EQ002);
_EQ002 = !_LC1_C16 & _LC3_C13;
-- Node name is ':2'
-- Equation name is '_LC4_C16', type is buried
_LC4_C16 = LCELL( _EQ003);
_EQ003 = _LC1_C16 & _LC3_C13 & !_LC8_C16;
-- Node name is ':3'
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = LCELL( _EQ004);
_EQ004 = !_LC2_C16 & _LC3_C13 & _LC8_C16;
-- Node name is ':4'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ005);
_EQ005 = _LC2_C16 & _LC3_C13;
-- Node name is ':24'
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = LCELL( _EQ006);
_EQ006 = _LC3_C16
# H;
-- Node name is '~35~1'
-- Equation name is '~35~1', location is LC4_C13, type is buried.
-- synthesized logic cell
_LC4_C13 = LCELL( _EQ007);
_EQ007 = _LC3_C13 & TJ
# DP & _LC3_C13;
-- Node name is ':36'
-- Equation name is '_LC5_C13', type is buried
!_LC5_C13 = _LC5_C13~NOT;
_LC5_C13~NOT = LCELL( _EQ008);
_EQ008 = _LC1_C13 & !_LC5_C13
# _LC1_C13 & _LC4_C13;
-- Node name is ':37'
-- Equation name is '_LC1_C13', type is buried
!_LC1_C13 = _LC1_C13~NOT;
_LC1_C13~NOT = LCELL( GD);
-- Node name is ':51'
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = LCELL( _EQ009);
_EQ009 = !_LC3_C16 & !TJ
# !H & !TJ;
Project Information d:\maxplus2\cpu_design\cpu_module\jiepai.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,145K
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