📄 cpumodel.rpt
字号:
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
ar3 | 26 83 | in0
ar4 | 27 82 | in1
ar5 | 28 81 | in2
ar6 | 29 80 | in3
ar7 | 30 79 | in4
d0 | 31 78 | in5
d1 | 32 77 | ^MSEL0
d2 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
d3 | 36 73 | in6
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
d d d G d t R R V R R R R G R V V G G G G G R R V R r r r G R R R R V i
4 5 6 N 7 1 E E C E E E E N E C C N N N N N E E C E 3 2 5 N E E E E C n
D S S C S S S S D S C C D D D D D S S C S D S S S S C 7
I E E I E E E E I E I I I I I I I E E I E I E E E E I
O R R O R R R R O R N N N N N N N R R O R O R R R R O
V V V V V V V T T T T T T T V V V V V V V
E E E E E E E E E E E E E E
D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\md\cpumodel.rpt
cpumodel
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A19 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 3/22( 13%)
A20 5/ 8( 62%) 2/ 8( 25%) 1/ 8( 12%) 1/2 1/2 5/22( 22%)
B1 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 2/2 11/22( 50%)
B2 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 2/2 15/22( 68%)
B3 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 6/22( 27%)
B4 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 1/2 9/22( 40%)
B5 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 6/22( 27%)
B7 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
B9 8/ 8(100%) 1/ 8( 12%) 8/ 8(100%) 1/2 1/2 8/22( 36%)
B10 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 2/2 2/2 20/22( 90%)
B11 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 1/2 12/22( 54%)
B12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 2/2 13/22( 59%)
B13 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 11/22( 50%)
B15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
B17 8/ 8(100%) 6/ 8( 75%) 6/ 8( 75%) 1/2 1/2 9/22( 40%)
B19 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 1/2 6/22( 27%)
B20 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
B21 5/ 8( 62%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
B22 7/ 8( 87%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 16/22( 72%)
B23 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
B24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
D1 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
D2 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
D3 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
D4 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 11/22( 50%)
D5 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
D6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
D7 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
D8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
D9 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
D10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/22( 50%)
D11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
D12 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 8/22( 36%)
D13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
D14 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
D15 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
D16 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
D17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
D18 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 13/22( 59%)
D19 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 10/22( 45%)
D20 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 8/22( 36%)
D21 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 11/22( 50%)
D22 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 8/22( 36%)
D23 7/ 8( 87%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 6/22( 27%)
D24 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
E2 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
E8 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 0/2 10/22( 45%)
E9 8/ 8(100%) 8/ 8(100%) 8/ 8(100%) 1/2 0/2 9/22( 40%)
E11 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
E13 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
E14 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
E15 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 9/22( 40%)
E16 7/ 8( 87%) 2/ 8( 25%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
E17 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 1/2 0/2 9/22( 40%)
E18 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
E19 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 10/22( 45%)
E20 8/ 8(100%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 10/22( 45%)
E21 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
E22 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
E23 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 10/22( 45%)
E24 6/ 8( 75%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
F7 7/ 8( 87%) 6/ 8( 75%) 7/ 8( 87%) 1/2 0/2 8/22( 36%)
F11 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
F14 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 1/2 17/22( 77%)
F15 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 11/22( 50%)
F16 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 0/2 0/2 17/22( 77%)
F19 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
F22 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 16/22( 72%)
F23 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
F24 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 1/2 15/22( 68%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
F25 8/8 (100%) 1/8 ( 12%) 7/8 ( 87%) 1/2 2/2 18/22( 81%)
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 48/96 ( 50%)
Total logic cells used: 487/1152 ( 42%)
Total embedded cells used: 8/48 ( 16%)
Total EABs used: 1/6 ( 16%)
Average fan-in: 3.03/4 ( 75%)
Total fan-in: 1477/4608 ( 32%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 28
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 487
Total flipflops required: 121
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 124/1152 ( 10%)
Logic Cell and Embedded Cell Counts
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -