kf_f.vhd

Fire&password数字系统实验

library ieee;
use ieee.std_logic_1164.all;

entity kf_f is
      port(A,B : in std_logic;
           C   : out std_logic);
end kf_f;

architecture kf_f_arc of kf_f is
      component knand2
         port(A,B  : in std_logic;
              C    : out std_logic);
      end component;
      signal tmp ,tmp1: std_logic;
begin
      U0 :knand2 port map(A,tmp,tmp1);
      U1 :knand2 port map(tmp1,B,tmp);
      C<=tmp;
end kf_f_arc;