📄 kcoun10.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity kcoun10 is
port(A : in std_logic;
B : out std_logic);
end kcoun10;
architecture kcoun10_arc of kcoun10 is
signal counter: std_logic;
begin
process(A)
variable counter1: integer range 0 to 15;
constant md : integer := 5;
begin
if(A 'event and A ='1')then
if(counter1 =md)then
counter1:=0;
counter <= not counter;
B <= counter;
end if;
counter1 := counter1+1;
end if;
end process;
end kcoun10_arc;
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