knand2.vhd

来自「Fire&password数字系统实验」· VHDL 代码 · 共 14 行

--description two inputs and_not gate description
library ieee;
use ieee.std_logic_1164.all;

entity knand2 is
      port(A,B  : in std_logic;
           C    : out std_logic);
end knand2;

architecture knand2_arc of knand2 is
begin
      C <= not (A and B);
end knand2_arc;