📄 kcoun102.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity kcoun102 is
port(A : in std_logic;
B : out std_logic);
end kcoun102;
architecture kcoun102_arc of kcoun102 is
component kcoun10
port(A : in std_logic;
B : out std_logic);
end component;
component kcoun20
port(A : in std_logic;
B : out std_logic);
end component;
signal tmp: std_logic;
begin
U0: kcoun10 port map(A,tmp);
U1: kcoun20 port map(tmp,B);
end kcoun102_arc;
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