ksy.vhd

来自「Fire&password数字系统实验」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;

entity ksy is
        port(A,B : in std_logic;
             C   : out std_logic);
end ksy;

architecture ksy_arc of ksy is
component kand2
    port(A,B  : in std_logic;
         C    : out std_logic);
end component;

component kdf
    port(A,B  : in std_logic;
         C,D  : out std_logic);
end component;

component knand2
    port(A,B  : in std_logic;
         C    : out std_logic);
end component;

signal TMP1,TMP2,TMP3,TMP4,TMP5,TMP6  : std_logic;

begin
U0: knand2   port map(A,TMP1,TMP2);
U1: knand2   port map(TMP2,TMP3,TMP1);
U2: kdf      port map(TMP2,B,TMP4,TMP3);
U3: kdf      port map(TMP4,B,TMP6,TMP5);
U4: kand2    port map(TMP4,TMP5,C);
end ksy_arc;