chang_control.rpt

Fire&password数字系统实验

  _EQ014 =  _LC5_B5
         #  A & !_LC5_B4
         #  _LC6_B5;

-- Node name is '|CONTROL:1|:17' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 =  A & !_LC5_B4
         #  _LC1_B6 &  _LC4_B6;

-- Node name is '|CONTROL:1|:19' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 = !A & !_LC5_B4
         #  _LC5_B4 &  _LC7_B5
         # !_LC3_B6 &  _LC5_B4;

-- Node name is '|CONTROL:1|:238' 
-- Equation name is '_LC3_B12', type is buried 
!_LC3_B12 = _LC3_B12~NOT;
_LC3_B12~NOT = LCELL( _EQ017);
  _EQ017 = !C & !D;

-- Node name is '|CONTROL:1|:463' 
-- Equation name is '_LC4_B12', type is buried 
_LC4_B12 = LCELL( _EQ018);
  _EQ018 =  E & !G & !_LC3_B12 &  _LC8_B2;

-- Node name is '|CONTROL:1|~470~1' 
-- Equation name is '_LC3_B2', type is buried 
-- synthesized logic cell 
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ019);
  _EQ019 = !_LC3_B4 &  _LC8_B2;

-- Node name is '|CONTROL:1|~488~1' 
-- Equation name is '_LC3_B4', type is buried 
-- synthesized logic cell 
!_LC3_B4 = _LC3_B4~NOT;
_LC3_B4~NOT = LCELL( _EQ020);
  _EQ020 = !_LC2_B4 &  _LC5_B4;

-- Node name is '|CONTROL:1|~488~2' 
-- Equation name is '_LC5_B2', type is buried 
-- synthesized logic cell 
_LC5_B2  = LCELL( _EQ021);
  _EQ021 = !E &  _LC8_B4
         #  _LC5_B12 & !_LC8_B4;

-- Node name is '|CONTROL:1|~488~3' 
-- Equation name is '_LC6_B2', type is buried 
-- synthesized logic cell 
_LC6_B2  = LCELL( _EQ022);
  _EQ022 =  _LC2_B2 & !_LC8_B2
         #  _LC4_B2 &  _LC5_B2 & !_LC8_B2;

-- Node name is '|CONTROL:1|~488~4' 
-- Equation name is '_LC7_B2', type is buried 
-- synthesized logic cell 
_LC7_B2  = LCELL( _EQ023);
  _EQ023 =  _LC2_B2 &  _LC3_B4
         #  _LC3_B4 &  _LC4_B2
         #  _LC6_B2;

-- Node name is '|CONTROL:1|:500' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ024);
  _EQ024 =  _LC8_B4
         #  _LC8_B2
         #  _LC5_B12;

-- Node name is '|CONTROL:1|~542~1' 
-- Equation name is '_LC2_B6', type is buried 
-- synthesized logic cell 
_LC2_B6  = LCELL( _EQ025);
  _EQ025 = !_LC8_B4
         #  E
         #  C
         # !D;

-- Node name is '|CONTROL:1|~542~2' 
-- Equation name is '_LC4_B6', type is buried 
-- synthesized logic cell 
_LC4_B6  = LCELL( _EQ026);
  _EQ026 =  _LC2_B4
         # !_LC5_B4
         #  _LC8_B2
         #  _LC2_B6;

-- Node name is '|CONTROL:1|~560~1' 
-- Equation name is '_LC1_B5', type is buried 
-- synthesized logic cell 
_LC1_B5  = LCELL( _EQ027);
  _EQ027 = !_LC5_B12 & !_LC8_B2
         # !_LC8_B2 &  _LC8_B4
         # !D &  _LC8_B2;

-- Node name is '|CONTROL:1|~560~2' 
-- Equation name is '_LC5_B5', type is buried 
-- synthesized logic cell 
_LC5_B5  = LCELL( _EQ028);
  _EQ028 =  _LC1_B5 &  _LC3_B5
         #  _LC3_B4 &  _LC3_B5
         #  _LC1_B5 &  _LC2_B5
         #  _LC2_B5 &  _LC3_B4;

-- Node name is '|CONTROL:1|~573~1' 
-- Equation name is '_LC1_B12', type is buried 
-- synthesized logic cell 
_LC1_B12 = LCELL( _EQ029);
  _EQ029 =  G & !_LC3_B12;

-- Node name is '|CONTROL:1|~583~1' 
-- Equation name is '_LC6_B4', type is buried 
-- synthesized logic cell 
_LC6_B4  = LCELL( _EQ030);
  _EQ030 = !C & !E &  _LC8_B4;

-- Node name is '|CONTROL:1|~588~1' 
-- Equation name is '_LC8_B12', type is buried 
-- synthesized logic cell 
_LC8_B12 = LCELL( _EQ031);
  _EQ031 =  F & !G & !_LC3_B12
         # !E & !G & !_LC3_B12;

-- Node name is '|CONTROL:1|~588~2' 
-- Equation name is '_LC2_B12', type is buried 
-- synthesized logic cell 
_LC2_B12 = LCELL( _EQ032);
  _EQ032 =  _LC8_B12
         #  C & !D;

-- Node name is '|CONTROL:1|~588~3' 
-- Equation name is '_LC1_B2', type is buried 
-- synthesized logic cell 
_LC1_B2  = LCELL( _EQ033);
  _EQ033 = !E &  _LC8_B4
         #  _LC2_B4
         #  _LC5_B12;

-- Node name is '|CONTROL:1|~590~1' 
-- Equation name is '_LC7_B12', type is buried 
-- synthesized logic cell 
_LC7_B12 = LCELL( _EQ034);
  _EQ034 = !F &  _LC4_B12
         #  E &  _LC8_B4;

-- Node name is '|CONTROL:1|~594~1' 
-- Equation name is '_LC7_B4', type is buried 
-- synthesized logic cell 
_LC7_B4  = LCELL( _EQ035);
  _EQ035 = !C &  _LC2_B4
         #  B &  _LC4_B4;

-- Node name is '|CONTROL:1|~596~1' 
-- Equation name is '_LC1_B4', type is buried 
-- synthesized logic cell 
_LC1_B4  = LCELL( _EQ036);
  _EQ036 =  _LC8_B2
         # !C &  _LC5_B12;



Project Information                     e:\cpu\fire&password\chang_control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 27,963K