📄 chang_control.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
23 - - B -- OUTPUT 0 1 0 0 H
24 - - B -- OUTPUT 0 1 0 0 I
22 - - B -- OUTPUT 0 1 0 0 J
66 - - B -- OUTPUT 0 1 0 0 K
21 - - B -- OUTPUT 0 1 0 0 L
25 - - B -- OUTPUT 0 1 0 0 M
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cpu\fire&password\chang_control.rpt
chang_control
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 04 DFFE + 2 1 0 1 |CONTROL:1|current_state~1
- 5 - B 12 DFFE + 2 1 0 5 |CONTROL:1|current_state~2
- 8 - B 04 DFFE + 1 3 0 8 |CONTROL:1|current_state~3
- 8 - B 02 DFFE + 1 2 0 11 |CONTROL:1|current_state~4
- 2 - B 04 DFFE + 1 2 0 6 |CONTROL:1|current_state~5
- 4 - B 02 AND2 s 1 1 0 2 |CONTROL:1|current_state~6~2
- 3 - B 06 AND2 s 1 1 0 2 |CONTROL:1|current_state~6~3
- 2 - B 05 AND2 s 0 4 0 1 |CONTROL:1|current_state~6~4
- 6 - B 05 OR2 s 2 2 0 1 |CONTROL:1|current_state~6~5
- 5 - B 04 DFFE + 2 1 0 9 |CONTROL:1|current_state~6
- 4 - B 05 DFFE + 0 3 1 0 |CONTROL:1|:9
- 6 - B 12 DFFE + 0 3 1 0 |CONTROL:1|:11
- 2 - B 02 DFFE + 2 2 1 2 |CONTROL:1|:13
- 3 - B 05 DFFE + 1 3 1 2 |CONTROL:1|:15
- 1 - B 06 DFFE + 1 2 1 0 |CONTROL:1|:17
- 8 - B 05 DFFE + 1 3 1 0 |CONTROL:1|:19
- 3 - B 12 AND2 ! 2 0 0 3 |CONTROL:1|:238
- 4 - B 12 AND2 2 2 0 2 |CONTROL:1|:463
- 3 - B 02 AND2 s ! 0 2 0 1 |CONTROL:1|~470~1
- 3 - B 04 AND2 s ! 0 2 0 4 |CONTROL:1|~488~1
- 5 - B 02 OR2 s 1 2 0 1 |CONTROL:1|~488~2
- 6 - B 02 OR2 s 0 4 0 1 |CONTROL:1|~488~3
- 7 - B 02 OR2 s 0 4 0 1 |CONTROL:1|~488~4
- 7 - B 05 OR2 0 3 0 2 |CONTROL:1|:500
- 2 - B 06 OR2 s 3 1 0 1 |CONTROL:1|~542~1
- 4 - B 06 OR2 s 0 4 0 1 |CONTROL:1|~542~2
- 1 - B 05 OR2 s 1 3 0 1 |CONTROL:1|~560~1
- 5 - B 05 OR2 s 0 4 0 1 |CONTROL:1|~560~2
- 1 - B 12 AND2 s 1 1 0 1 |CONTROL:1|~573~1
- 6 - B 04 AND2 s 2 1 0 2 |CONTROL:1|~583~1
- 8 - B 12 OR2 s 3 1 0 1 |CONTROL:1|~588~1
- 2 - B 12 OR2 s 2 1 0 1 |CONTROL:1|~588~2
- 1 - B 02 OR2 s 1 3 0 1 |CONTROL:1|~588~3
- 7 - B 12 OR2 s 2 2 0 1 |CONTROL:1|~590~1
- 7 - B 04 OR2 s 2 2 0 1 |CONTROL:1|~594~1
- 1 - B 04 OR2 s 1 2 0 1 |CONTROL:1|~596~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\cpu\fire&password\chang_control.rpt
chang_control
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 13/ 48( 27%) 0/ 48( 0%) 2/16( 12%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cpu\fire&password\chang_control.rpt
chang_control
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 12 clk
Device-Specific Information: e:\cpu\fire&password\chang_control.rpt
chang_control
** EQUATIONS **
A : INPUT;
B : INPUT;
C : INPUT;
clk : INPUT;
D : INPUT;
E : INPUT;
F : INPUT;
G : INPUT;
-- Node name is 'H'
-- Equation name is 'H', type is output
H = _LC4_B5;
-- Node name is 'I'
-- Equation name is 'I', type is output
I = _LC6_B12;
-- Node name is 'J'
-- Equation name is 'J', type is output
J = _LC2_B2;
-- Node name is 'K'
-- Equation name is 'K', type is output
K = _LC3_B5;
-- Node name is 'L'
-- Equation name is 'L', type is output
L = _LC1_B6;
-- Node name is 'M'
-- Equation name is 'M', type is output
M = _LC8_B5;
-- Node name is '|CONTROL:1|current_state~1'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = D & _LC1_B4
# !B & _LC4_B4;
-- Node name is '|CONTROL:1|current_state~2'
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC7_B12
# !C & !D & _LC5_B12;
-- Node name is '|CONTROL:1|current_state~3'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !D & _LC6_B4
# _LC1_B12 & _LC8_B2;
-- Node name is '|CONTROL:1|current_state~4'
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC2_B12 & _LC8_B2
# C & _LC1_B2;
-- Node name is '|CONTROL:1|current_state~5'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC7_B4
# A & !_LC5_B4;
-- Node name is '|CONTROL:1|current_state~6~2'
-- Equation name is '_LC4_B2', type is buried
-- synthesized logic cell
_LC4_B2 = LCELL( _EQ006);
_EQ006 = C & _LC5_B4;
-- Node name is '|CONTROL:1|current_state~6~3'
-- Equation name is '_LC3_B6', type is buried
-- synthesized logic cell
_LC3_B6 = LCELL( _EQ007);
_EQ007 = B & !_LC2_B4;
-- Node name is '|CONTROL:1|current_state~6~4'
-- Equation name is '_LC2_B5', type is buried
-- synthesized logic cell
_LC2_B5 = LCELL( _EQ008);
_EQ008 = _LC3_B6 & _LC5_B4 & !_LC8_B2 & !_LC8_B4;
-- Node name is '|CONTROL:1|current_state~6~5'
-- Equation name is '_LC6_B5', type is buried
-- synthesized logic cell
_LC6_B5 = LCELL( _EQ009);
_EQ009 = C & _LC3_B5 & !_LC8_B2
# !D & _LC3_B5 & !_LC8_B2;
-- Node name is '|CONTROL:1|current_state~6'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = _LC5_B4 & !_LC6_B4
# !D & _LC5_B4
# A & !_LC6_B4
# A & !D;
-- Node name is '|CONTROL:1|:9'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !_LC2_B4 & _LC5_B4 & _LC7_B5;
-- Node name is '|CONTROL:1|:11'
-- Equation name is '_LC6_B12', type is buried
_LC6_B12 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = _LC3_B4 & _LC6_B12
# _LC6_B12 & !_LC8_B2
# !_LC3_B4 & _LC4_B12;
-- Node name is '|CONTROL:1|:13'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = C & !D & !_LC3_B2
# _LC7_B2;
-- Node name is '|CONTROL:1|:15'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
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