time.fit.qmsg

数字秒表的设计

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.012 ns register register " "Info: Estimated most critical path is register to register delay of 3.012 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt:inst6\|cqi\[1\] 1 REG LAB_X11_Y16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y16; Fanout = 4; REG Node = 'cnt:inst6\|cqi\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst6|cqi[1] } "NODE_NAME" } "" } } { "cnt.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/cnt.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.442 ns) 1.466 ns xianshi:inst7\|dout~629 2 COMB LAB_X12_Y14 1 " "Info: 2: + IC(1.024 ns) + CELL(0.442 ns) = 1.466 ns; Loc. = LAB_X12_Y14; Fanout = 1; COMB Node = 'xianshi:inst7\|dout~629'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "1.466 ns" { cnt:inst6|cqi[1] xianshi:inst7|dout~629 } "NODE_NAME" } "" } } { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 2.130 ns xianshi:inst7\|dout~630 3 COMB LAB_X12_Y14 1 " "Info: 3: + IC(0.372 ns) + CELL(0.292 ns) = 2.130 ns; Loc. = LAB_X12_Y14; Fanout = 1; COMB Node = 'xianshi:inst7\|dout~630'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.664 ns" { xianshi:inst7|dout~629 xianshi:inst7|dout~630 } "NODE_NAME" } "" } } { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.275 ns) + CELL(0.607 ns) 3.012 ns xianshi:inst7\|dout\[1\] 4 REG LAB_X12_Y14 7 " "Info: 4: + IC(0.275 ns) + CELL(0.607 ns) = 3.012 ns; Loc. = LAB_X12_Y14; Fanout = 7; REG Node = 'xianshi:inst7\|dout\[1\]'" {  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "0.882 ns" { xianshi:inst7|dout~630 xianshi:inst7|dout[1] } "NODE_NAME" } "" } } { "xianshi.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/xianshi.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.341 ns 44.52 % " "Info: Total cell delay = 1.341 ns ( 44.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.671 ns 55.48 % " "Info: Total interconnect delay = 1.671 ns ( 55.48 % )" {  } {  } 0}  } { { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "3.012 ns" { cnt:inst6|cqi[1] xianshi:inst7|dout~629 xianshi:inst7|dout~630 xianshi:inst7|dout[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 23 16:29:52 2008 " "Info: Processing ended: Mon Jun 23 16:29:52 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}