time.fit.qmsg

数字秒表的设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 23 16:29:45 2008 " "Info: Processing started: Mon Jun 23 16:29:45 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off time -c time " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off time -c time" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "time EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"time\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 28" {  } { { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 112 0 168 128 "clk" "" } { 72 536 568 88 "clk" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkgen:inst\|clk_scan Global clock " "Info: Automatically promoted signal \"clkgen:inst\|clk_scan\" to use Global clock" {  } { { "clkgen.vhd" "" { Text "D:/cyclone/fpga/成功完成/数字秒表的设计/clkgen.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cnt:inst1\|reduce_nor~0 Global clock " "Info: Automatically promoted signal \"cnt:inst1\|reduce_nor~0\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst1\|reduce_nor~0" } } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst1|reduce_nor~0 } "NODE_NAME" } "" } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" "" { cnt:inst1|reduce_nor~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cnt:inst2\|reduce_nor~0 Global clock " "Info: Automatically promoted signal \"cnt:inst2\|reduce_nor~0\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst2\|reduce_nor~0" } } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst2|reduce_nor~0 } "NODE_NAME" } "" } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" "" { cnt:inst2|reduce_nor~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cnt:inst4\|reduce_nor~0 Global clock " "Info: Automatically promoted signal \"cnt:inst4\|reduce_nor~0\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst4\|reduce_nor~0" } } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst4|reduce_nor~0 } "NODE_NAME" } "" } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" "" { cnt:inst4|reduce_nor~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cnt:inst3\|reduce_nor~0 Global clock " "Info: Automatically promoted signal \"cnt:inst3\|reduce_nor~0\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst3\|reduce_nor~0" } } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst3|reduce_nor~0 } "NODE_NAME" } "" } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" "" { cnt:inst3|reduce_nor~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cnt:inst5\|reduce_nor~0 Global clock " "Info: Automatically promoted signal \"cnt:inst5\|reduce_nor~0\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cnt:inst5\|reduce_nor~0" } } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { cnt:inst5|reduce_nor~0 } "NODE_NAME" } "" } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" "" { cnt:inst5|reduce_nor~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clr Global clock " "Info: Automatically promoted signal \"clr\" to use Global clock" {  } { { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 240 0 168 256 "clr" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clr " "Info: Pin \"clr\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "time.bdf" "" { Schematic "D:/cyclone/fpga/成功完成/数字秒表的设计/time.bdf" { { 240 0 168 256 "clr" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clr" } } } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" "" { Report "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time_cmp.qrpt" Compiler "time" "UNKNOWN" "V1" "D:/cyclone/fpga/成功完成/数字秒表的设计/db/time.quartus_db" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/" "" "" { clr } "NODE_NAME" } "" } } { "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" { Floorplan "D:/cyclone/fpga/成功完成/数字秒表的设计/time.fld" "" "" { clr } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}