rece_7e.v

HDLC控制接收数据开始标志7E和去零模块

`timescale 1ns / 1ps
/*/////////////////////////////////////////////////////////////////////////////////
// Company: 盛和科技
// Engineer: 刘书超
// 
// Create Date:    16:28:06 03/05/2008 
// Design Name: 
// Module Name:    rece_7E 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description:    首先将输入的并行8位数据通过移位寄存器转变为1位串行数据，通过状态机
//                 检测开始标志7E，当检测到开始7E时，开始数据的去零和检测结束标志7E，
//                 同时输出8位数据。
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
/////////////////////////////////////////////////////////////////////////////////*/
module rece_7E(data,clk,rst,CHCLK,data_out,start_7E,z,error);
   
  input          clk,
                 rst,
                 CHCLK;
  input   [7:0]  data;
                 
  output  [7:0]  data_out;
  output         start_7E;        //start_7E为开始标志7E的输出
  output         z;               //当start_7E为7E时，Z为1
  
  output         error;           //当检测到连续的7个1时，error置位，数据重发
                 
  reg     [2:0]  state1;
  reg     [3:0]  state2;
  reg     [2:0]  count;

  reg     [7:0]  _data_out,       //_data_out为数据输出的中间寄存器，
                 shift_out,       //shift_out为输出数据移位寄存器
                 _out,           //_out为检测开始7E中间寄存器
                 start_7E,       
                 shift_data;     //_data为输入数据中间移位寄存器
                                                             
  reg            out_data,        //out_data为检测后数据输出的中间寄存器,1位
                 z,
                 x;              //X为数据并串转换后输入检测去零状态机的中间寄存器
					  
  parameter  IDLE=3'd0, A=3'd1,B=3'd2,C=3'd3,D=3'd4,E=3'd5,F=3'd6,G=3'd7;
  parameter  DLE=4'd8,AB=4'd9,BC=4'd10,CD=4'd11,DE=4'd12,EF=4'd13,FG=4'd14;
  
  always@(posedge clk)
    begin
      if(rst|shift_out=='h7E)          //shift_out为7E时，输出数据信号Z置低
        begin
        z        <= 0;
        start_7E <= 0;
        end
      else
        if(state1=='d7&&x==0)
          begin
          start_7E <= 'h7E;
          z        <= 1;
          end
    end
  
  always@(posedge clk)               //检测开始标志字7E
    begin
      if(rst)
        begin
        state1 <= IDLE;                 //state1表示检测开始标志块的状态
        state2 <= DLE;                  //state2表示检测去0块的状态  
	      end
      else
        if(z==0)
          begin
          casex(state1)
            IDLE:  if(x==0)
                     state1 <= A;
                   else
                     state1 <= IDLE;
               A:  if(x==1)
                     state1 <= B;
                   else
                     state1 <= IDLE;
               B:  if(x==1)
                     state1 <= C;
                   else
                     state1 <= IDLE;
               C:  if(x==1)
                     state1 <= D;
                   else
                     state1 <= IDLE;
               D:  if(x==1)
                     state1 <= E;
                   else
                     state1 <= IDLE;
               E:  if(x==1)
                     state1 <= F;
                   else
                     state1 <= IDLE;
               F:  if(x==1)
                     state1 <= G;
                   else
                     state1 <= IDLE;
               G:  if(x==0)
                     state1 <= IDLE;
            default: state1 <= IDLE;
          endcase
          end
    end
  
  /*
  输入数据进行移位转换，data为输入8位，x为输入转换后的一位串行数据
  */
  always@(posedge clk) 
    begin
      if(rst)
        shift_data <= 0;
      else
        if(CHCLK)
          begin
          shift_data <= data;
          x          <= data[7];
          end
        else
          begin
          shift_data <= shift_data<<1;
          x          <= shift_data[6];
          end
    end
  
  always@(posedge clk)
    begin
      if(rst)
        begin
        count     <= 3'b110;
        shift_out <= 0;
        end
      else
        if(!(state2==EF&&x==0)&&z==1)                   //  传送数据
          begin
          shift_out    <= shift_out<<1;                    //输出数据移位寄存器
          shift_out[0] <= out_data;
          count        <= count+1;                 //通过count计数满8位，使数据8位输出
          end
    end
  
  /*
  /输出中间移位寄存器来判断是否输出数据，当不为7E时输出8位数据
  */
  always@(posedge clk)
    begin
    if(rst)
      _data_out <= 0;
    else
      if(!(shift_out==8'h7E) && z==1 && count==3'd7)
        _data_out <= shift_out;                  //如果计算7E之间的数据，在此进行计数
    end
  
  assign  data_out = _data_out;
  
  always@(posedge clk)     //检测数据去0和结束标志7E
    begin
      if(rst)
        out_data <= 0;
      else
        if(z==1)
          casex(state2)
            DLE: if(x==1)
                   begin
                   state2   <= AB;
                   out_data <= x;
                   end
                 else
                   begin
                   state2   <= DLE;
                   out_data <= x;
                   end
             AB: if(x==1)
                   begin
                   state2   <= BC;
                   out_data <= x;
                   end
                 else
                   begin
                   state2   <= DLE;
                   out_data <= x;
                   end
             BC: if(x==1)
                   begin
                   state2   <= CD;
                   out_data <= x;
                   end
                 else
                   begin
                   state2   <= DLE;
                   out_data <= x;
                   end
             CD: if(x==1)
                   begin
                   state2   <= DE;
                   out_data <= x;
                   end
                 else
                   begin
                   state2   <= DLE;
                   out_data <= x;
                   end
             DE: if(x==1)
                   begin
                   state2   <= EF;
                   out_data <= x;
                   end
                 else
                   begin
                   state2   <= DLE;
                   out_data <= x;
                   end
             EF: if(x==0)            //检测到5个1，1个0，去0传送数据
                   state2   <= DLE;
                 else
                   begin
                   state2   <= FG;
                   out_data <= x;
                   end
             FG: if(x==0)
                   begin
                   state2   <= DLE;
                   out_data <= x;
                   end
          default:state2<=DLE;
        endcase
    end
  /*
  当检测到7个连续的1，使error置位，数据重发
  */
  assign  error = (state2==FG&&x==1)?1:0;
  
endmodule