decoder2_4.vhd

来自「数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY decoder2_4 IS
PORT (A,B,EN: in std_logic;
      Q: out std_logic_vector(3 downto 0));
END decoder2_4;
ARCHITECTURE rt1 OF decoder2_4 IS
SIGNAL dz:std_logic_vector(1 downto 0);
BEGIN  
dz<=B&A;
PROCESS (EN,dz)
BEGIN
   IF EN='0' THEN
   	CASE dz IS
		WHEN "00"=>Q<="1110";
		WHEN "01"=>Q<="1101";
		WHEN "10"=>Q<="1011";
		WHEN "11"=>Q<="0111";
      END CASE;
   ELSE
	Q<="ZZZZ";
   END IF;
END PROCESS;
END rt1;