moore.vhd

来自「数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器」· VHDL 代码 · 共 62 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Moore IS
port (  cp	:	in std_logic;
		con	:   in std_logic;
		state:	out std_logic_vector(1 downto 0);
		flag:	out std_logic);
	end Moore;
	
	architecture behave of Moore IS
	signal PresentState,NextState:integer range 0 to 3:=0;
	begin
		switchToNextState: Process(cp)
		begin
			if rising_edge(cp) then
				PresentState<=NextState;
			end if;
		end Process switchToNextState;
		ChangeStateMode :Process(con,PresentState)
		begin
			case PresentState IS
			when 0=>
				if con='0' then
					NextState<=0;
				else
					NextState<=1;
				end if;
				flag<='0';
				
			when 1=>
				if con='0' then
					NextState<=1;
				else
					NextState<=2;
				end if;
				flag<='0';
			when 2=>
				if con='0' then
					NextState<=2;
				else
					NextState<=3;
				end if;
				flag<='0';

			when 3=>
				if con='0' then
					NextState<=3;
				else
					NextState<=0;
				end if;
				flag<='1';
				
			when others=>
				NextState<=0;
				flag<='0';
			end case;
			state<=conv_std_logic_vector(PresentState,2);
		end process;
	end behave;