count_10.vhd

来自「数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count_10 IS
port (clk,clr,en:in std_logic;
	 qa,qb,qc,qd:out std_logic);
end count_10;
	
architecture behave of count_10 IS
signal q:std_logic_vector(3 downto 0);
begin
		qa<=q(3);qb<=q(2);qc<=q(1);qd<=q(0);
process(en,clr,clk)
	begin
		if rising_edge(clk) then
			if(clr='1') then
				q<="0000";
			elsif (en='0')then
				q<=q;
				elsif (q<"1001") then
					q<=q+'1';
					else
						q<="0000";
			end if;
		end if;			
end process;	
end behave;