allplus.vhd

来自「数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器」· VHDL 代码 · 共 14 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ALLPLUS IS
PORT (A,B,Ci_1: in std_logic;
      Si,Ci : out std_logic);
END ALLPLUS;
ARCHITECTURE behave OF ALLPLUS IS
BEGIN
PROCESS(A,B,Ci_1)
BEGIN
   Si<=A XOR B XOR Ci_1;
   Ci<=(A AND B)OR(A AND Ci_1)OR(B AND Ci_1);
END PROCESS;
END behave;