test_cpu.v

A Relatively Simple RISC CPU 设计源码并附详细的说明文档。可以ModelSim进行仿真

`include "ram.v"
`include "rom.v"
`include "addr_decode.v"
`include "cpu_top.v"
`timescale 1ns / 100ps
`define PERIOD 100                 // matches clk_gen.v
module t;
  reg reset_req,clock;
  integer test;
  reg [(3*8):0] mnemonic;          //array that holds 3 8-bit ASCII characters
  reg [12:0] PC_addr,IR_addr;
  wire [7:0] data;
  wire [12:0] addr;
  wire rd,wr,halt,ram_sel,rom_sel;
//----------------------------------------------------------------------------
cpu   t_cpu (.clk(clock),.reset(reset_req),.halt(halt),.rd(rd),
                                       .wr(wr),.addr(addr),.data(data));

ram   t_ram  (.addr(addr[9:0]),.read(rd),.write(wr),.ena(ram_sel),.data(data));

rom   t_rom  (.addr(addr),.read(rd),.ena(rom_sel),.data(data));

addr_decode   t_addr_decode (.addr(addr),.ram_sel(ram_sel),.rom_sel(rom_sel));
endmodule