machinectl.v

来自「A Relatively Simple RISC CPU 设计源码并附详细的说明」· Verilog 代码 · 共 16 行

module machinectl( ena, fetch, rst);
output  ena;
input  fetch, rst;
reg ena;

always @(posedge fetch or posedge rst)
   begin
      if(rst)
         ena<=0;
      else
         ena<=1;
   end

endmodule