datactl.v

来自「A Relatively Simple RISC CPU 设计源码并附详细的说明」· Verilog 代码 · 共 10 行

module datactl (data,in,data_ena);
output [7:0]data;
input [7:0]in;
input data_ena;

assign  data = (data_ena)? in : 8'bzzzz_zzzz;

endmodule