osc_display.v

verilog编写基于FPGA的示波器核心实现

module osc_display(
					clk,
					cs,
					datain,
					RDADDR,
					x_out,
					y_out,
					da_wrx,
					da_wry
					);
input clk;
input cs;
input [7:0] datain;
output reg [9:0] RDADDR;
output [7:0] x_out;
output [7:0] y_out;
output reg da_wrx,da_wry;

reg link_xout,link_yout;
reg [12:0] counttemp;
reg [2:0] bittemp;
reg [7:0] xbuf;
reg [7:0] ybuf;

parameter 	GET			=	10'b0_000_000_001,
			COMPARE1	=	10'b0_000_000_010,
			COMPARE2	=	10'b0_000_000_100,	
			COMPARE3	=	10'b0_000_001_000,	
			COMPARE4	=	10'b0_000_010_000,	
			COMPARE5	=	10'b0_000_100_000,
			COMPARE6	=	10'b0_001_000_000,
			COMPARE7	=	10'b0_010_000_000,
			COMPARE8	=	10'b0_100_000_000,
			NEWCOUNT	=	10'b1_000_000_000;

reg [9:0] state;

assign x_out=link_xout?xbuf:8'bz;
assign y_out=link_yout?ybuf:8'bz;

always @(posedge clk)
begin
if (cs)
	begin
	state<=GET;
	link_xout<=0;
	link_yout<=0;
	counttemp<=0;
	bittemp<=0;
	da_wrx<=1;
	da_wry<=1;
	end
else
	begin
	link_xout<=1;
	link_yout<=1;	
	case (state)
	default:	begin							//GET
				RDADDR<=counttemp[12:3];
				bittemp<=7-counttemp[2:0];
				state<=COMPARE1;
				da_wrx<=1;
				da_wry<=1;
				end
	COMPARE1:	begin
				da_wrx<=0;
				da_wry<=0;
				if (datain[bittemp])
					begin
					xbuf<={counttemp[6:0],1'b0};
					ybuf<={counttemp[12:7],1'b0};
					state<=COMPARE2;
					end
				else
					begin
					xbuf<=0;
					ybuf<=0;
					state<=NEWCOUNT;
					end
				end	
	COMPARE2:	begin
				da_wrx<=1;
				da_wry<=1;				
				state<=COMPARE3;
				end

	COMPARE3:	begin
				state<=COMPARE4;
				end

	COMPARE4:	begin
				state<=COMPARE5;
				end
	/*COMPARE5:	begin
				state<=COMPARE6;
				end
	COMPARE6:	begin
				state<=COMPARE7;
				end
	COMPARE7:	begin
				state<=COMPARE8;
				end		*/										
	COMPARE5:	begin
				state<=NEWCOUNT;
				end							
	NEWCOUNT:	begin
				state<=GET;
				if (counttemp==8191) 
					counttemp<=0;
				else 	
					counttemp<=counttemp+13'b1;								
				end			
	endcase
	end
end

endmodule