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📄 phase_test.sim.rpt

📁 verilog编写基于fpga的鉴相器模块
💻 RPT
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; |phase_control|phase_test:inst|Equal0~171                                                              ; |phase_control|phase_test:inst|Equal0~171                                                                               ; combout          ;
; |phase_control|phase_test:inst|Equal0~173                                                              ; |phase_control|phase_test:inst|Equal0~173                                                                               ; combout          ;
; |phase_control|phase_test:inst|counttemp[3]                                                            ; |phase_control|phase_test:inst|counttemp[3]~152COUT1_163                                                                ; cout1            ;
; |phase_control|phase_test:inst|Equal0~174                                                              ; |phase_control|phase_test:inst|Equal0~174                                                                               ; combout          ;
; |phase_control|phase_test:inst|counttemp[5]                                                            ; |phase_control|phase_test:inst|counttemp[5]~154COUT1_165                                                                ; cout1            ;
; |phase_control|phase_test:inst|Equal0~176                                                              ; |phase_control|phase_test:inst|Equal0~176                                                                               ; combout          ;
; |phase_control|phase_test:inst|counttemp[6]                                                            ; |phase_control|phase_test:inst|counttemp[6]~159COUT1_166                                                                ; cout1            ;
; |phase_control|phase_test:inst|Equal0~178                                                              ; |phase_control|phase_test:inst|Equal0~178                                                                               ; combout          ;
; |phase_control|phase_test:inst|Equal0~179                                                              ; |phase_control|phase_test:inst|Equal0~179                                                                               ; combout          ;
; |phase_control|phase_test:inst|PLLEN                                                                   ; |phase_control|phase_test:inst|PLLEN                                                                                    ; regout           ;
; |phase_control|phase_test:inst|countstart~632                                                          ; |phase_control|phase_test:inst|countstart~632                                                                           ; combout          ;
; |phase_control|phase_test:inst|gatelim[15]~998                                                         ; |phase_control|phase_test:inst|gatelim[15]~998                                                                          ; combout          ;
; |phase_control|phase_test:inst|countstart~633                                                          ; |phase_control|phase_test:inst|countstart~633                                                                           ; combout          ;
; |phase_control|clk                                                                                     ; |phase_control|clk                                                                                                      ; combout          ;
; |phase_control|cs_phase                                                                                ; |phase_control|cs_phase                                                                                                 ; combout          ;
; |phase_control|phaseinA                                                                                ; |phase_control|phaseinA                                                                                                 ; combout          ;
; |phase_control|phaseinB                                                                                ; |phase_control|phaseinB                                                                                                 ; combout          ;
; |phase_control|phase_sig[1]                                                                            ; |phase_control|phase_sig[1]                                                                                             ; combout          ;
; |phase_control|phase_sig[0]                                                                            ; |phase_control|phase_sig[0]                                                                                             ; combout          ;
; |phase_control|gatein[2]                                                                               ; |phase_control|gatein[2]                                                                                                ; combout          ;
; |phase_control|gatein[5]                                                                               ; |phase_control|gatein[5]                                                                                                ; combout          ;
; |phase_control|gatein[6]                                                                               ; |phase_control|gatein[6]                                                                                                ; combout          ;
+--------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                               ; Output Port Name                                                                                                         ; Output Port Type ;
+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+------------------+
; |phase_control|phase_test:inst|COUNTNUM[31]                                                             ; |phase_control|phase_test:inst|COUNTNUM[31]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[30]                                                             ; |phase_control|phase_test:inst|COUNTNUM[30]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[29]                                                             ; |phase_control|phase_test:inst|COUNTNUM[29]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[28]                                                             ; |phase_control|phase_test:inst|COUNTNUM[28]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[27]                                                             ; |phase_control|phase_test:inst|COUNTNUM[27]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[26]                                                             ; |phase_control|phase_test:inst|COUNTNUM[26]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[25]                                                             ; |phase_control|phase_test:inst|COUNTNUM[25]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[24]                                                             ; |phase_control|phase_test:inst|COUNTNUM[24]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[23]                                                             ; |phase_control|phase_test:inst|COUNTNUM[23]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[22]                                                             ; |phase_control|phase_test:inst|COUNTNUM[22]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[21]                                                             ; |phase_control|phase_test:inst|COUNTNUM[21]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[20]                                                             ; |phase_control|phase_test:inst|COUNTNUM[20]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[19]                                                             ; |phase_control|phase_test:inst|COUNTNUM[19]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[18]                                                             ; |phase_control|phase_test:inst|COUNTNUM[18]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[17]                                                             ; |phase_control|phase_test:inst|COUNTNUM[17]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[16]                                                             ; |phase_control|phase_test:inst|COUNTNUM[16]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[15]                                                             ; |phase_control|phase_test:inst|COUNTNUM[15]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[14]                                                             ; |phase_control|phase_test:inst|COUNTNUM[14]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[13]                                                             ; |phase_control|phase_test:inst|COUNTNUM[13]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[12]                                                             ; |phase_control|phase_test:inst|COUNTNUM[12]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[11]                                                             ; |phase_control|phase_test:inst|COUNTNUM[11]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[10]                                                             ; |phase_control|phase_test:inst|COUNTNUM[10]                                                                              ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[9]                                                              ; |phase_control|phase_test:inst|COUNTNUM[9]                                                                               ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[8]                                                              ; |phase_control|phase_test:inst|COUNTNUM[8]                                                                               ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[5]                                                              ; |phase_control|phase_test:inst|COUNTNUM[5]                                                                               ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[4]                                                              ; |phase_control|phase_test:inst|COUNTNUM[4]                                                                               ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[2]                                                              ; |phase_control|phase_test:inst|COUNTNUM[2]                                                                               ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[1]                                                              ; |phase_control|phase_test:inst|COUNTNUM[1]                                                                               ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[0]                                                              ; |phase_control|phase_test:inst|COUNTNUM[0]                                                                               ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[31]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[30] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella30~COUT        ; cout             ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella29~COUT        ; cout0            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[29] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella29~COUTCOUT1_2 ; cout1            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella28~COUT        ; cout0            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[28] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella28~COUTCOUT1_2 ; cout1            ;

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