phase_test.sim.rpt

verilog编写基于fpga的鉴相器模块

; Display missing 0-value coverage report                                                    ; On             ; On            ;
; Detect setup and hold time violations                                                      ; Off            ; Off           ;
; Detect glitches                                                                            ; Off            ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off            ; Off           ;
; Generate Signal Activity File                                                              ; Off            ; Off           ;
; Group bus channels in simulation results                                                   ; Off            ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On             ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE     ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off            ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off            ;               ;
; Glitch Filtering                                                                           ; Off            ; Off           ;
+--------------------------------------------------------------------------------------------+----------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      20.59 % ;
; Total nodes checked                                 ; 173          ;
; Total output ports checked                          ; 238          ;
; Total output ports with complete 1/0-value coverage ; 49           ;
; Total output ports with no 1/0-value coverage       ; 178          ;
; Total output ports with no 1-value coverage         ; 179          ;
; Total output ports with no 0-value coverage         ; 188          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                         ;
+--------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                              ; Output Port Name                                                                                                        ; Output Port Type ;
+--------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------+------------------+
; |phase_control|phase_test:inst|countstop                                                               ; |phase_control|phase_test:inst|countstop                                                                                ; regout           ;
; |phase_control|phase_test:inst|COUNTNUM[31]~32                                                         ; |phase_control|phase_test:inst|COUNTNUM[31]~32                                                                          ; combout          ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[6] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella6~COUT        ; cout0            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[5] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[5]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[5] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella5~COUT        ; cout             ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[4] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella4~COUTCOUT1_2 ; cout1            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[3] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella3~COUTCOUT1_2 ; cout1            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[2] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella2~COUTCOUT1_2 ; cout1            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[1] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella1~COUTCOUT1_2 ; cout1            ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[0] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[0]                  ; regout           ;
; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|safe_q[0] ; |phase_control|phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated|counter_cella0~COUT        ; cout             ;
; |phase_control|phase_pll:inst12|altpll:altpll_component|_clk0                                          ; |phase_control|phase_pll:inst12|altpll:altpll_component|_clk0                                                           ; clk0             ;
; |phase_control|inst10                                                                                  ; |phase_control|inst10                                                                                                   ; combout          ;
; |phase_control|phase_test:inst|sclr                                                                    ; |phase_control|phase_test:inst|sclr                                                                                     ; regout           ;
; |phase_control|phase_test:inst|countstart                                                              ; |phase_control|phase_test:inst|countstart                                                                               ; regout           ;
; |phase_control|phase_test:inst|counttemp[4]                                                            ; |phase_control|phase_test:inst|counttemp[4]~144COUT1_164                                                                ; cout1            ;
; |phase_control|phase_test:inst|counttemp[1]                                                            ; |phase_control|phase_test:inst|counttemp[1]~145                                                                         ; cout0            ;
; |phase_control|phase_test:inst|counttemp[1]                                                            ; |phase_control|phase_test:inst|counttemp[1]~145COUT1_162                                                                ; cout1            ;
; |phase_control|phase_test:inst|Equal0~169                                                              ; |phase_control|phase_test:inst|Equal0~169                                                                               ; combout          ;
; |phase_control|phase_test:inst|counttemp[2]                                                            ; |phase_control|phase_test:inst|counttemp[2]~148                                                                         ; cout             ;
; |phase_control|phase_test:inst|counttemp[0]                                                            ; |phase_control|phase_test:inst|counttemp[0]~149                                                                         ; cout0            ;
; |phase_control|phase_test:inst|counttemp[0]                                                            ; |phase_control|phase_test:inst|counttemp[0]~149COUT1_161                                                                ; cout1            ;