📄 phase_test.map.rpt
字号:
; E2_PH ; 0 ; Untyped ;
; E3_PH ; 0 ; Untyped ;
; M_PH ; 0 ; Untyped ;
; C1_USE_CASC_IN ; 0 ; Untyped ;
; C2_USE_CASC_IN ; 0 ; Untyped ;
; C3_USE_CASC_IN ; 0 ; Untyped ;
; C4_USE_CASC_IN ; 0 ; Untyped ;
; C5_USE_CASC_IN ; 0 ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; Cyclone ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT0 ; PORT_UNUSED ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_USED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE1 ; PORT_UNUSED ; Untyped ;
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Aug 19 20:48:56 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phase_test -c phase_test
Info: Found 1 design units, including 1 entities, in source file ../phase_test.v
Info: Found entity 1: phase_test
Info: Found 1 design units, including 1 entities, in source file ../phase_control.bdf
Info: Found entity 1: phase_control
Info: Elaborating entity "phase_control" for the top level hierarchy
Info: Elaborating entity "phase_test" for hierarchy "phase_test:inst"
Info (10264): Verilog HDL Case Statement information at phase_test.v(45): all case item expressions in this case statement are onehot
Warning (10230): Verilog HDL assignment warning at phase_test.v(83): truncated value with size 32 to match size of target (16)
Warning: Using design file phase_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: phase_counter
Info: Elaborating entity "phase_counter" for hierarchy "phase_counter:inst1"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "phase_counter:inst1|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "phase_counter:inst1|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_2ii.tdf
Info: Found entity 1: cntr_2ii
Info: Elaborating entity "cntr_2ii" for hierarchy "phase_counter:inst1|lpm_counter:lpm_counter_component|cntr_2ii:auto_generated"
Warning: Using design file phase_pll.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: phase_pll
Info: Elaborating entity "phase_pll" for hierarchy "phase_pll:inst12"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "phase_pll:inst12|altpll:altpll_component"
Info: Elaborated megafunction instantiation "phase_pll:inst12|altpll:altpll_component"
Info: State machine "|phase_control|phase_test:inst|state" contains 2 states
Info: Selected Auto state machine encoding method for state machine "|phase_control|phase_test:inst|state"
Info: Encoding result for state machine "|phase_control|phase_test:inst|state"
Info: Completed encoding using 1 state bits
Info: Encoded state bit "phase_test:inst|state.COUNT"
Info: State "|phase_control|phase_test:inst|state.IDLE" uses code string "0"
Info: State "|phase_control|phase_test:inst|state.COUNT" uses code string "1"
Info: Implemented 173 device resources after synthesis - the final resource count might be different
Info: Implemented 22 input pins
Info: Implemented 32 output pins
Info: Implemented 118 logic cells
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Processing ended: Sun Aug 19 20:48:59 2007
Info: Elapsed time: 00:00:03
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