sram_control.smp_dump.txt

verilog编写fpga与片外SRAM通信模块

State Machine - |sram_control|state
Name state.RD_ADDRNEW state.RD_DATANEW state.WR_ADDRNEW state.WR_DATANEW state.READY state.IDLE 
state.IDLE 0 0 0 0 0 0 
state.WR_ADDRNEW 0 0 1 0 0 1 
state.RD_ADDRNEW 1 0 0 0 0 1 
state.WR_DATANEW 0 0 0 1 0 1 
state.READY 0 0 0 0 1 1 
state.RD_DATANEW 0 1 0 0 0 1