sram_control.hif

verilog编写fpga与片外SRAM通信模块

Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1760
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
sram_control
# storage
db|sram_control.(0).cnf
db|sram_control.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sram_control.v
cba9b82eab262b9fe63f12a764844058
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
IDLE
0000001
PARAMETER_BIN
DEF
READY
0000010
PARAMETER_BIN
DEF
WR_DATANEW
0000100
PARAMETER_BIN
DEF
WR_ADDRNEW
0001000
PARAMETER_BIN
DEF
RD_DATANEW
0010000
PARAMETER_BIN
DEF
RD_ADDRNEW
0100000
PARAMETER_BIN
DEF
YES
1
PARAMETER_BIN
DEF
NO
0
PARAMETER_BIN
DEF
}
# hierarchies {
|
}
# end
# complete