prev_cmp_clock.map.qmsg

基于VHDL的电子钟 实现一个简单的电子钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 09 17:24:49 2008 " "Info: Processing started: Wed Apr 09 17:24:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-clock_display " "Info: Found design unit 1: clock-clock_display" {  } { { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "F:/quartus2/shiyan3/clock.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock_pkg.vhd 1 0 " "Info: Found 1 design units, including 0 entities, in source file clock_pkg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock_pkg " "Info: Found design unit 1: clock_pkg" {  } { { "clock_pkg.vhd" "" { Text "F:/quartus2/shiyan3/clock_pkg.vhd" 5 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt60-cnt60_display " "Info: Found design unit 1: cnt60-cnt60_display" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt60 " "Info: Found entity 1: cnt60" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hour.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hour.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hour-hour_display " "Info: Found design unit 1: hour-hour_display" {  } { { "hour.vhd" "" { Text "F:/quartus2/shiyan3/hour.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 hour " "Info: Found entity 1: hour" {  } { { "hour.vhd" "" { Text "F:/quartus2/shiyan3/hour.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt60 cnt60:sec " "Info: Elaborating entity \"cnt60\" for hierarchy \"cnt60:sec\"" {  } { { "clock.vhd" "sec" { Text "F:/quartus2/shiyan3/clock.vhd" 19 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2011_UNCONVERTED" "carry cnt60.vhd(17) " "Error (10818): Can't infer register for \"carry\" at cnt60.vhd(17) because it does not hold its value outside the clock edge" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 17 0 0 } }  } 0 10818 "Can't infer register for \"%1!s!\" at %2!s! because it does not hold its value outside the clock edge" 0 0 "" 0}
{ "Error" "EVRFX_VDB_2015_UNCONVERTED" "cnt60.vhd(17) " "Error (10822): HDL error at cnt60.vhd(17): couldn't implement registers for assignments on this clock edge" {  } { { "cnt60.vhd" "" { Text "F:/quartus2/shiyan3/cnt60.vhd" 17 0 0 } }  } 0 10822 "HDL error at %1!s!: couldn't implement registers for assignments on this clock edge" 0 0 "" 0}
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "cnt60:sec " "Error: Can't elaborate user hierarchy \"cnt60:sec\"" {  } { { "clock.vhd" "sec" { Text "F:/quartus2/shiyan3/clock.vhd" 19 0 0 } }  } 0 0 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed Apr 09 17:24:53 2008 " "Error: Processing ended: Wed Apr 09 17:24:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:04 " "Error: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}