clock.tan.qmsg

基于VHDL的电子钟 实现一个简单的电子钟

{ "Info" "ITDB_TH_RESULT" "show\[0\]~reg0 x clk2 -6.208 ns register " "Info: th for register \"show\[0\]~reg0\" (data pin = \"x\", clock pin = \"clk2\") is -6.208 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 2.740 ns + Longest register " "Info: + Longest clock path from clock \"clk2\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk2 1 CLK PIN_17 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 18; CLK Node = 'clk2'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/lenovo/桌面/shiyan3/clock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns show\[0\]~reg0 2 REG LC_X12_Y6_N5 1 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y6_N5; Fanout = 1; REG Node = 'show\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { clk2 show[0]~reg0 } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/lenovo/桌面/shiyan3/clock.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk2 show[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk2 clk2~out0 show[0]~reg0 } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "clock.vhd" "" { Text "C:/Documents and Settings/lenovo/桌面/shiyan3/clock.vhd" 58 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.963 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns x 1 PIN PIN_103 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_103; Fanout = 7; PIN Node = 'x'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/lenovo/桌面/shiyan3/clock.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.016 ns) + CELL(0.478 ns) 8.963 ns show\[0\]~reg0 2 REG LC_X12_Y6_N5 1 " "Info: 2: + IC(7.016 ns) + CELL(0.478 ns) = 8.963 ns; Loc. = LC_X12_Y6_N5; Fanout = 1; REG Node = 'show\[0\]~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.494 ns" { x show[0]~reg0 } "NODE_NAME" } } { "clock.vhd" "" { Text "C:/Documents and Settings/lenovo/桌面/shiyan3/clock.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 21.72 % ) " "Info: Total cell delay = 1.947 ns ( 21.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.016 ns ( 78.28 % ) " "Info: Total interconnect delay = 7.016 ns ( 78.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.963 ns" { x show[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.963 ns" { x x~out0 show[0]~reg0 } { 0.000ns 0.000ns 7.016ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { clk2 show[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { clk2 clk2~out0 show[0]~reg0 } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.963 ns" { x show[0]~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.963 ns" { x x~out0 show[0]~reg0 } { 0.000ns 0.000ns 7.016ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 15:09:02 2008 " "Info: Processing ended: Wed May 07 15:09:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}