day.vhd

来自「基于VHDL的电子钟 实现一个简单的电子钟」· VHDL 代码 · 共 67 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity day is 
port( 	dh,dl: buffer std_logic_vector (3 downto 0);
      	clk : in std_logic;
        carry2: in std_logic_vector (1 downto 0);
	    carry1: buffer std_logic
         );
end day;
architecture day_display of day is
begin 
  process(clk,carry2)
  begin
	if clk'event  and clk='1' then
	if carry2="00" then carry1<=not carry1;
	
	elsif carry2="10" then  
	if dl=9 then
		dl <="0000";
		dh <= dh+1;
	  elsif dl=8 then 
		if dh=2 then
		  dh <= "0000"; dl <="0000";
                  carry1 <= not carry1;
		else dl <= dl+ 1;
                     carry1 <= '0';
		end if;
	  else dl <= dl+1;
               carry1 <= '0';
	  end if;
	elsif carry2="01" then
	if dl=9 then
		dl <="0000";
		dh <= dh+1;
	  elsif dl=0then 
		if dh=3then
		  dh <= "0000"; dl <="0000";
                  carry1 <= not carry1;
		else dl <= dl+ 1;
                     carry1 <= '0';
		end if;
	  else dl <= dl+1;
               carry1 <= '0';
	  end if;
	elsif carry2="11" then
	if dl=9 then
		dl <="0000";
		dh <= dh+1;
	  elsif dl=1then 
		if dh=3then
		  dh <= "0000"; dl <="0000";
                  carry1 <= not carry1;
		else dl <= dl+ 1;
                     carry1 <= '0';
		end if;
	  else dl <= dl+1;
               carry1 <= '0';
	  end if;
	
	end if;
	end if;
    
   end process;
end day_display;