year.vhd

来自「基于VHDL的电子钟 实现一个简单的电子钟」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity year is 
port( 	yh,yl : buffer std_logic_vector (3 downto 0);
      	clk : in std_logic
	 );
end year;
architecture year_display of year is
begin 
  process(clk)
  begin
	if clk'event  and clk='1' then
	  if yl=9 then
		yl <="0000";
		yh <= yh+1;
	  else yl <= yl+1;
	  end if;
	end if;
  end process;
end year_display;