hour.vhd

来自「基于VHDL的电子钟 实现一个简单的电子钟」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hour is 
port( 	hh,hl : buffer std_logic_vector (3 downto 0);
      	clk : in std_logic;
	carry: buffer std_logic  );  
end hour;
architecture hour_display of hour is
begin 
  process(clk)
  begin
	if clk'event  and clk='1' then
	  if hl=9 then
		hl <="0000";
		hh <= hh+1;
	  elsif hl=3 then 
		if hh=2 then
		  hh <= "0000"; hl <="0000";
                  carry <= not carry;
		else hl <= hl+ 1;
                     carry <= '0';
		end if;
	  else hl <= hl+1;
               carry <= '0';
	  end if;
	end if;
  end process;
end hour_display;